add top_uart

10 files changed, 250 insertions, 0 deletions

diff --git a/pnr/top_uart/makefile b/pnr/top_uart/makefile
new file mode 100644
index 0000000..cbb853c
--- /dev/null
+++ b/pnr/top_uart/makefile
@@ -0,0 +1,10 @@
+
+PROJECT = top_uart
+
+# Take the vhdl files of the project
+# from the simulation setup. This defines SYN_SOURCE_FILES
+include ../../sim/$(PROJECT)/makefile.sources
+# List all files for the project
+SOURCE_FILES = $(SYN_SOURCE_FILES)
+
+include ../makefile
diff --git a/pnr/top_uart/top_uart_pins.tcl b/pnr/top_uart/top_uart_pins.tcl
new file mode 100644
index 0000000..8f89eb8
--- /dev/null
+++ b/pnr/top_uart/top_uart_pins.tcl
@@ -0,0 +1,42 @@
+# assign pin locations to a quartus project
+
+set_location_assignment PIN_L22 -to SW[0]
+set_location_assignment PIN_L21 -to SW[1]
+set_location_assignment PIN_M22 -to SW[2]
+set_location_assignment PIN_V12 -to SW[3]
+set_location_assignment PIN_W12 -to SW[4]
+set_location_assignment PIN_U12 -to SW[5]
+set_location_assignment PIN_U11 -to SW[6]
+set_location_assignment PIN_M2 -to SW[7]
+set_location_assignment PIN_M1 -to SW[8]
+set_location_assignment PIN_L2 -to SW[9]
+set_location_assignment PIN_R20 -to LEDR[0]
+set_location_assignment PIN_R19 -to LEDR[1]
+set_location_assignment PIN_U19 -to LEDR[2]
+set_location_assignment PIN_Y19 -to LEDR[3]
+set_location_assignment PIN_T18 -to LEDR[4]
+set_location_assignment PIN_V19 -to LEDR[5]
+set_location_assignment PIN_Y18 -to LEDR[6]
+set_location_assignment PIN_U18 -to LEDR[7]
+set_location_assignment PIN_R18 -to LEDR[8]
+set_location_assignment PIN_R17 -to LEDR[9]
+set_location_assignment PIN_R22 -to KEY[0]
+set_location_assignment PIN_R21 -to KEY[1]
+set_location_assignment PIN_T22 -to KEY[2]
+set_location_assignment PIN_T21 -to KEY[3]
+set_location_assignment PIN_L1 -to CLOCK_50
+set_location_assignment PIN_U22 -to LEDG[0]
+set_location_assignment PIN_U21 -to LEDG[1]
+set_location_assignment PIN_V22 -to LEDG[2]
+set_location_assignment PIN_V21 -to LEDG[3]
+# This is expansion port 1 GPI_1 from scripts/de1_pin_assignments_minimumio.tcl
+set_location_assignment PIN_H12 -to EXP[0]
+set_location_assignment PIN_H13 -to EXP[1]
+set_location_assignment PIN_H14 -to EXP[2]
+set_location_assignment PIN_G15 -to EXP[3]
+set_location_assignment PIN_E14 -to EXP[4]
+set_location_assignment PIN_E15 -to EXP[5]
+set_location_assignment PIN_F15 -to EXP[6]
+set_location_assignment PIN_G16 -to EXP[7]
+set_location_assignment PIN_F14 -to UART_RXD
+set_location_assignment PIN_G12 -to UART_TXD
diff --git a/sim/top_uart/makefile b/sim/top_uart/makefile
new file mode 100644
index 0000000..5f96c0c
--- /dev/null
+++ b/sim/top_uart/makefile
@@ -0,0 +1,9 @@
+PROJECT = top_uart
+
+# This include must define SYN_SOURCE_FILES
+include ./makefile.sources
+
+SOURCE_FILES = $(SYN_SOURCE_FILES) \
+../../src/t_$(PROJECT).vhd
+
+include ../makefile
diff --git a/sim/top_uart/makefile.sources b/sim/top_uart/makefile.sources
new file mode 100644
index 0000000..c5493f3
--- /dev/null
+++ b/sim/top_uart/makefile.sources
@@ -0,0 +1,7 @@
+# All files which synthesized
+
+SYN_SOURCE_FILES = \
+../../src/baudcnt.vhd \
+../../src/edge.vhd \
+../../src/uart_tx_shift.vhd \
+../../src/top_uart.vhd
diff --git a/sim/top_uart/view_signals.gtkw b/sim/top_uart/view_signals.gtkw
new file mode 100644
index 0000000..272ac13
--- /dev/null
+++ b/sim/top_uart/view_signals.gtkw
@@ -0,0 +1,27 @@
+[*]
+[*] GTKWave Analyzer v3.3.118 (w)1999-2023 BSI
+[*] Tue May 14 14:13:35 2024
+[*]
+[dumpfile] "/home/caeuser/projects/dtlab/sim/top_uart/t_top_uart.ghw"
+[dumpfile_mtime] "Tue May 14 14:10:01 2024"
+[dumpfile_size] 2003
+[savefile] "/home/caeuser/projects/dtlab/sim/top_uart/view_signals.gtkw"
+[timestart] 0
+[size] 1170 600
+[pos] 38 -78
+*-28.012674 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] top.
+[treeopen] top.t_top_uart.
+[sst_width] 245
+[signals_width] 169
+[sst_expanded] 1
+[sst_vpaned_height] 259
+@28
+top.t_top_uart.sim_clk
+top.t_top_uart.sim_rst_n
+@22
+#{top.t_top_uart.sim_sw[9:0]} top.t_top_uart.sim_sw[9] top.t_top_uart.sim_sw[8] top.t_top_uart.sim_sw[7] top.t_top_uart.sim_sw[6] top.t_top_uart.sim_sw[5] top.t_top_uart.sim_sw[4] top.t_top_uart.sim_sw[3] top.t_top_uart.sim_sw[2] top.t_top_uart.sim_sw[1] top.t_top_uart.sim_sw[0]
+@28
+top.t_top_uart.sim_x
+[pattern_trace] 1
+[pattern_trace] 0
diff --git a/src/baudcnt.vhd b/src/baudcnt.vhd
new file mode 100644
index 0000000..4e18aa7
--- /dev/null
+++ b/src/baudcnt.vhd
@@ -0,0 +1,16 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity baudcnt is
+  port (
+    clk     : in std_ulogic;
+    rst_n   : in std_ulogic;
+    start_i : in std_ulogic;
+    en_o    : out std_ulogic);
+end entity;
+
+architecture rtl of baudcnt is
+begin
+
+end architecture rtl;
+
diff --git a/src/t_top_uart.vhd b/src/t_top_uart.vhd
new file mode 100644
index 0000000..ddec0cb
--- /dev/null
+++ b/src/t_top_uart.vhd
@@ -0,0 +1,75 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity t_top_uart is
+end entity;
+
+architecture beh of t_top_uart is
+
+  signal sim_clk     : std_ulogic;
+  signal sim_rst_n   : std_ulogic;
+  signal sim_x       : std_ulogic;
+  signal sim_uart_rxd  : std_ulogic;
+  signal sim_uart_txd  : std_ulogic;
+
+  signal sim_sw      : std_ulogic_vector(9 downto 0);
+  signal sim_key     : std_ulogic_vector(3 downto 0);
+  signal sim_ledr    : std_ulogic_vector(9 downto 0);
+  signal sim_ledg    : std_ulogic_vector(3 downto 0);
+  signal sim_exp     : std_ulogic_vector(7 downto 0);
+
+  signal simstop : boolean := false;
+
+begin
+
+  -- Stimuli clock generator
+  clk_p : process
+  begin
+    sim_clk <= '0';
+    wait for 10 ns;
+    sim_clk <= '1';
+    wait for 10 ns;
+    if simstop then
+      wait;
+    end if;
+  end process;
+
+  -- Stimuli reset generator
+  sim_rst_n <= '0', '1' after 55 ns;
+
+  -- UART input - not used...
+  sim_uart_rxd <= '0';
+
+  -- Stimuli key push
+  stim_p : process
+  begin
+    sim_x <= '0';
+    wait until rising_edge(sim_rst_n);
+    wait for 200 ns;
+    sim_x <= '1';
+    wait for 100 ns;
+    sim_x <= '0';
+    wait for 600 ns;
+    simstop <= true;
+    wait;
+  end process ;
+
+  top_uart_inst: entity work.top_uart
+   port map(
+      SW       => sim_sw,
+      KEY      => sim_key,
+      CLOCK_50 => sim_clk,
+      UART_RXD => sim_uart_rxd,
+      UART_TXD => sim_uart_txd,
+      EXP      => sim_exp,
+      LEDG     => sim_ledg,
+      LEDR     => sim_ledr
+  );
+
+  -- Connect stimuli to input signals
+  sim_key(0) <= sim_rst_n;
+  sim_key(1) <= sim_x;
+  sim_key(3 downto 2) <= "00";
+  sim_sw <= "0001000111";
+
+end architecture beh;
\ No newline at end of file
diff --git a/src/top_uart.vhd b/src/top_uart.vhd
new file mode 100644
index 0000000..4cc6c01
--- /dev/null
+++ b/src/top_uart.vhd
@@ -0,0 +1,37 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity top_uart is 
+port ( SW       : in  std_ulogic_vector(9 downto 0);
+       KEY      : in  std_ulogic_vector(3 downto 0);
+       CLOCK_50 : in  std_ulogic;
+       UART_RXD : in  std_ulogic;
+       UART_TXD : out std_ulogic;
+       EXP      : out std_ulogic_vector(7 downto 0);
+       LEDG     : out std_ulogic_vector(3 downto 0);
+       LEDR     : out std_ulogic_vector(9 downto 0));
+end entity;
+
+architecture rtl of top_uart is
+  signal clk     : std_ulogic;
+  signal rst_n   : std_ulogic;
+  signal en, txd : std_ulogic;
+begin
+  -- Assign the inputs to signals with reasonable names
+  clk <= CLOCK_50;
+  rst_n <= KEY(0);
+
+  txd <= '0';
+  en <= '0';
+
+  -- Set the outputs;
+  EXP(7 downto 4) <= "0000";
+  EXP(3 downto 0) <= (3 => txd,
+          2 => en,
+          1 => rst_n,
+          0 => clk);
+  UART_TXD <= txd;
+  LEDR <= SW;
+  LEDG <= KEY;
+
+end architecture rtl;
\ No newline at end of file
diff --git a/src/uart_tx_shift.vhd b/src/uart_tx_shift.vhd
new file mode 100644
index 0000000..b81fe78
--- /dev/null
+++ b/src/uart_tx_shift.vhd
@@ -0,0 +1,18 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity uart_tx_shift is
+  port (
+    clk     : in std_ulogic;
+    rst_n   : in std_ulogic;
+    start_i : in std_ulogic;
+    en_i    : in std_ulogic;
+    d_i     : in std_ulogic_vector(7 downto 0);
+    tx_o    : out std_ulogic);
+end entity;
+
+architecture rtl of uart_tx_shift is
+begin
+
+end architecture rtl;
+
diff --git a/vhdl_ls.toml b/vhdl_ls.toml
index d162b4d..2460aad 100644
--- a/vhdl_ls.toml
+++ b/vhdl_ls.toml
@@ -22,4 +22,13 @@ top_count.files = [
     ,'src/pwm.vhd'
     ,'src/top_count.vhd'
     ,'src/t_top_count.vhd'
+    ]
+
+
+top_uart.files = [
+    'src/edge.vhd'
+    ,'src/baudcnt.vhd'
+    ,'src/uart_tx_shift.vhd'
+    ,'src/top_uart.vhd'
+    ,'src/t_top_uart.vhd'
     ]
\ No newline at end of file