add top_shift and simulation

9 files changed, 349 insertions, 0 deletions

diff --git a/pnr/top_shift/makefile b/pnr/top_shift/makefile
new file mode 100644
index 0000000..e9a612d
--- /dev/null
+++ b/pnr/top_shift/makefile
@@ -0,0 +1,10 @@
+
+PROJECT = top_shift
+
+# Take the vhdl files of the project
+# from the simulation setup. This defines SYN_SOURCE_FILES
+include ../../sim/$(PROJECT)/makefile.sources
+# List all files for the project
+SOURCE_FILES = $(SYN_SOURCE_FILES)
+
+include ../makefile
diff --git a/pnr/top_shift/top_shift_pins.tcl b/pnr/top_shift/top_shift_pins.tcl
new file mode 100644
index 0000000..b35b1fb
--- /dev/null
+++ b/pnr/top_shift/top_shift_pins.tcl
@@ -0,0 +1,40 @@
+# assign pin locations to a quartus project
+
+set_location_assignment PIN_L22 -to SW[0]
+set_location_assignment PIN_L21 -to SW[1]
+set_location_assignment PIN_M22 -to SW[2]
+set_location_assignment PIN_V12 -to SW[3]
+set_location_assignment PIN_W12 -to SW[4]
+set_location_assignment PIN_U12 -to SW[5]
+set_location_assignment PIN_U11 -to SW[6]
+set_location_assignment PIN_M2 -to SW[7]
+set_location_assignment PIN_M1 -to SW[8]
+set_location_assignment PIN_L2 -to SW[9]
+set_location_assignment PIN_R20 -to LEDR[0]
+set_location_assignment PIN_R19 -to LEDR[1]
+set_location_assignment PIN_U19 -to LEDR[2]
+set_location_assignment PIN_Y19 -to LEDR[3]
+set_location_assignment PIN_T18 -to LEDR[4]
+set_location_assignment PIN_V19 -to LEDR[5]
+set_location_assignment PIN_Y18 -to LEDR[6]
+set_location_assignment PIN_U18 -to LEDR[7]
+set_location_assignment PIN_R18 -to LEDR[8]
+set_location_assignment PIN_R17 -to LEDR[9]
+set_location_assignment PIN_R22 -to KEY[0]
+set_location_assignment PIN_R21 -to KEY[1]
+set_location_assignment PIN_T22 -to KEY[2]
+set_location_assignment PIN_T21 -to KEY[3]
+set_location_assignment PIN_L1 -to CLOCK_50
+set_location_assignment PIN_U22 -to LEDG[0]
+set_location_assignment PIN_U21 -to LEDG[1]
+set_location_assignment PIN_V22 -to LEDG[2]
+set_location_assignment PIN_V21 -to LEDG[3]
+# This is expansion port 1 GPI_1 from scripts/de1_pin_assignments_minimumio.tcl
+set_location_assignment PIN_H12 -to EXP[0]
+set_location_assignment PIN_H13 -to EXP[1]
+set_location_assignment PIN_H14 -to EXP[2]
+set_location_assignment PIN_G15 -to EXP[3]
+set_location_assignment PIN_E14 -to EXP[4]
+set_location_assignment PIN_E15 -to EXP[5]
+set_location_assignment PIN_F15 -to EXP[6]
+set_location_assignment PIN_G16 -to EXP[7]
\ No newline at end of file
diff --git a/sim/makefile b/sim/makefile
new file mode 100644
index 0000000..9eb77b1
--- /dev/null
+++ b/sim/makefile
@@ -0,0 +1,128 @@
+## ----------------------------------------------------------------------------
+## Script     : makefile
+## ----------------------------------------------------------------------------
+## Author(s)  : Johann Faerber, Friedrich Beckmann
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: This makefile allows automating design flow with ModelSim,
+##              it is based on a design directory structure shown at 
+##              the end of this file.
+## ----------------------------------------------------------------------------
+
+GHDL_CMD = ghdl
+GHDL_OPTIONS  = --std=08 --workdir=work
+LOG_FILE = ghdl.log
+
+ECHO_TARGET := echo "$$@"  >> $(LOG_FILE) 2>&1
+TIME_STAMP := echo "$$@ $$(date --iso=seconds)"
+TIME_STAMP_LOG_FILE := echo "$$@ $$(date --iso=seconds)" >> $(LOG_FILE) 2>&1
+
+###################################################################
+# Main Targets
+#
+###################################################################
+
+#==== Default target - running simulation without drawing waveforms ====#
+.PHONY : sim
+sim : t_$(PROJECT).ghw
+
+#==== WAVEFORM DRAWING ====#
+.PHONY : wave
+wave : t_$(PROJECT).ghw
+	@echo "---- $@"  >> $(LOG_FILE) 2>&1
+	@$(TIME_STAMP_LOG_FILE)
+	@gtkwave t_$(PROJECT).ghw view_signals.gtkw  >> $(LOG_FILE) 2>&1 &
+
+#==== SIMULATION ====#
+t_$(PROJECT).ghw : .compile.done
+	@echo "---- $@"  >> $(LOG_FILE) 2>&1
+	@$(TIME_STAMP_LOG_FILE)
+	@echo "Simulating ..."  2>&1 | tee -a $(LOG_FILE)
+	@$(GHDL_CMD) -r $(GHDL_OPTIONS) t_$(PROJECT) --wave=t_$(PROJECT).ghw >> $(LOG_FILE) 2>&1
+	@$(TIME_STAMP) > .sim.done
+
+#==== COMPILATION ====#
+compile : .compile.done
+
+.compile.done : $(SOURCE_FILES) .gproject.done
+	@echo "---- $@"  >> $(LOG_FILE) 2>&1
+	@$(TIME_STAMP_LOG_FILE)
+	@echo "Compiling ..."  >> $(LOG_FILE) 2>&1
+	@$(GHDL_CMD) -m $(GHDL_OPTIONS) --warn-default-binding t_$(PROJECT) 2>&1 | tee -a $(LOG_FILE)
+	@$(TIME_STAMP) > .compile.done
+
+#==== PROJECT CREATION ====#
+gproject : .gproject.done
+
+.gproject.done : makefile.sources
+	@echo "---- $@"  >> $(LOG_FILE) 2>&1
+	@$(TIME_STAMP_LOG_FILE)
+	@echo "Creating Project ..."  >> $(LOG_FILE) 2>&1
+	@rm -rf ./ghdl_sources.tcl
+	@# Create a directory work if it does not exist. Otherwise do nothing.
+	@[ -d work ] || mkdir -p work
+	@$(GHDL_CMD) -i $(GHDL_OPTIONS) $(SOURCE_FILES) 2>&1 | tee -a $(LOG_FILE) 
+	@$(TIME_STAMP) > .gproject.done
+
+#==== Synthesis Check ====#
+synthcheck : .compile.done
+	@echo "---- $@"  >> $(LOG_FILE) 2>&1
+	@$(TIME_STAMP_LOG_FILE)
+	@echo "Synthesis Check ..."  >> $(LOG_FILE) 2>&1
+	@$(GHDL_CMD) --synth --out=none $(GHDL_OPTIONS) $(PROJECT) 2>&1 | tee -a $(LOG_FILE)
+	@$(TIME_STAMP) > .synth.done
+
+warnings: $(LOG_FILE)
+	@echo "---- $@"  >> $(LOG_FILE) 2>&1
+	@$(TIME_STAMP_LOG_FILE)
+	@grep "Warning (" $(LOG_FILE)
+
+.PHONY : clean
+clean:
+	@$(GHDL_CMD) --remove; rm -rf work*.cf work *.vcd *.ghw *.log ghdl_sources.tcl .gproject.done .compile.done .sim.done .synth.done
+
+help:
+	@echo 'Default target is sim'
+	@echo '  "make gproject" to create a new ghdl project only'
+	@echo '  "make compile" to compile all VHDL sources in batch mode'
+	@echo '  "make sim" to run ghdl with the top testbench of the project'
+	@echo '  "make wave" to display the simulation results in the time domain'
+	@echo '  "make clean" to remove all generated files'
+
+
+## ----------------------------------------------------------------------------
+## Description: 
+## ------------
+## assumes the following design directory structure as prerequisite
+## 
+## DigitaltechnikPraktikum
+## |   
+## +---src
+## |       and2gate_equation.vhd
+## |       invgate_equation.vhd
+## |       mux2to1_structure.vhd
+## |       or2gate_equation.vhd
+## |       t_mux2to1.vhd
+## |       de1_mux2to1_structure.vhd
+## |
+## +---sim
+## |   |   makefile
+## |   |
+## |   \---mux2to1
+## |           makefile
+## |           makefile.sources
+## |
+## +---pnr
+## |   |   makefile
+## |   |
+## |   \---de1_mux2to1
+## |           de1_mux2to1_pins.tcl
+## |           makefile
+## |
+## \---scripts
+##         de1_pin_assignments_minimumio.csv
+##         de1_pin_assignments_minimumio.tcl
+##         modelsim.ini
+##         quartus_project_settings.tcl
+## ----------------------------------------------------------------------------
+
diff --git a/sim/top_shift/makefile b/sim/top_shift/makefile
new file mode 100644
index 0000000..9b0a862
--- /dev/null
+++ b/sim/top_shift/makefile
@@ -0,0 +1,9 @@
+PROJECT = top_shift
+
+# This include must define SYN_SOURCE_FILES
+include ./makefile.sources
+
+SOURCE_FILES = $(SYN_SOURCE_FILES) \
+../../src/t_$(PROJECT).vhd
+
+include ../makefile
diff --git a/sim/top_shift/makefile.sources b/sim/top_shift/makefile.sources
new file mode 100644
index 0000000..460360c
--- /dev/null
+++ b/sim/top_shift/makefile.sources
@@ -0,0 +1,4 @@
+# All files which synthesized
+
+SYN_SOURCE_FILES = \
+../../src/top_shift.vhd
diff --git a/sim/top_shift/view_signals.gtkw b/sim/top_shift/view_signals.gtkw
new file mode 100644
index 0000000..8437be3
--- /dev/null
+++ b/sim/top_shift/view_signals.gtkw
@@ -0,0 +1,34 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Wed Mar  6 22:54:48 2024
+[*]
+[dumpfile] "/home/caeuser/projects/dtlab/sim/top_shift/t_top_shift.ghw"
+[dumpfile_mtime] "Wed Mar  6 22:52:36 2024"
+[dumpfile_size] 1314
+[savefile] "/home/caeuser/projects/dtlab/sim/top_shift/view_signals.gtkw"
+[timestart] 0
+[size] 1000 600
+[pos] -1 -1
+*-26.740849 115500000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] top.
+[treeopen] top.t_top_shift.
+[treeopen] top.t_top_shift.dut.
+[sst_width] 245
+[signals_width] 173
+[sst_expanded] 1
+[sst_vpaned_height] 185
+@28
+top.t_top_shift.dut.clk
+top.t_top_shift.dut.rst_n
+top.t_top_shift.dut.x
+@800028
+#{top.t_top_shift.dut.sr[0:1]} top.t_top_shift.dut.sr[0] top.t_top_shift.dut.sr[1]
+@28
+top.t_top_shift.dut.sr[0]
+top.t_top_shift.dut.sr[1]
+@1001200
+-group_end
+@29
+top.t_top_shift.dut.y
+[pattern_trace] 1
+[pattern_trace] 0
diff --git a/src/t_top_shift.vhd b/src/t_top_shift.vhd
new file mode 100644
index 0000000..996b6d1
--- /dev/null
+++ b/src/t_top_shift.vhd
@@ -0,0 +1,65 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity t_top_shift is
+end entity;
+
+architecture beh of t_top_shift is
+
+  signal sim_clk     : std_ulogic;
+  signal sim_rst_n   : std_ulogic;
+  signal sim_x       : std_ulogic;
+  signal sim_y       : std_ulogic;
+
+  signal sim_sw      : std_ulogic_vector(9 downto 0);
+  signal sim_key     : std_ulogic_vector(3 downto 0);
+  signal sim_ledr    : std_ulogic_vector(9 downto 0);
+  signal sim_ledg    : std_ulogic_vector(3 downto 0);
+  signal sim_exp     : std_ulogic_vector(7 downto 0);
+
+  signal simstop : boolean := false;
+
+begin
+
+  -- Stimuli clock generator
+  clk_p : process
+  begin
+    sim_clk <= '0';
+    wait for 10 ns;
+    sim_clk <= '1';
+    wait for 10 ns;
+    if simstop then
+      wait;
+    end if;
+  end process;
+
+  -- Stimuli reset generator
+  sim_rst_n <= '0', '1' after 55 ns;
+
+  -- Stimuli key push
+  sim_x <= '0', '1' after 135 ns, '0' after 195 ns;
+
+  -- Simulation stopper
+  simstop <= true after 300 ns;
+
+  -- Device under test instantiation
+  dut : entity work.top_shift
+   port map(
+      SW   => sim_sw,
+      KEY  => sim_key,
+      CLOCK_50 => sim_clk,
+      EXP  => sim_exp,
+      LEDG => sim_ledg,
+      LEDR => sim_ledr
+  );
+
+  -- Connect stimuli to input signals
+  sim_key(0) <= sim_rst_n;
+  sim_key(1) <= sim_x;
+  sim_key(3 downto 2) <= "00";
+  sim_sw <= "1010000101";
+
+  -- Check the expansion port y output
+  sim_y <= sim_exp(3);
+ 
+end architecture beh;
\ No newline at end of file
diff --git a/src/top_shift.vhd b/src/top_shift.vhd
new file mode 100644
index 0000000..f6036bc
--- /dev/null
+++ b/src/top_shift.vhd
@@ -0,0 +1,55 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity top_shift is 
+port ( SW       : in  std_ulogic_vector(9 downto 0);
+       KEY      : in  std_ulogic_vector(3 downto 0);
+       CLOCK_50 : in  std_ulogic;
+       EXP      : out std_ulogic_vector(7 downto 0);
+       LEDG     : out std_ulogic_vector(3 downto 0);
+       LEDR     : out std_ulogic_vector(9 downto 0));
+end entity;
+
+architecture rtl of top_shift is
+  signal clk     : std_ulogic;
+  signal rst_n   : std_ulogic;
+  signal x       : std_ulogic;
+  signal sr, srnext : std_ulogic_vector(0 to 1);
+  signal en       : std_ulogic;
+begin
+  -- Assign the inputs to signals with reasonable names
+  clk <= CLOCK_50;
+  rst_n <= KEY(0);
+  x <= KEY(1);
+
+  -------------------------
+  -- The edge detector
+  -------------------------
+  -- Designpattern Register
+  -- Create a register with two flipflops with low active
+  -- asynchronous reset.
+  -- D-Input is connected to srnext
+  -- Q Outputs are connected to sr
+  sr <= "00" when rst_n = '0' else srnext when rising_edge(clk);
+
+  -- Implement the shift register function with next state logic
+  srnext(0) <= x;
+  srnext(1) <= sr(0);
+
+  -- Compute the output function from the shift register content
+  en <= sr(0) xor sr(1);
+
+  --------------------------
+  -- New code here
+  --------------------------
+
+  -- Set the outputs;
+  EXP <= (7 downto 4 => '0',
+          3 => en,
+          2 => x,
+          1 => rst_n,
+          0 => clk);
+  LEDR <= SW;
+  LEDG <= KEY;
+
+end architecture rtl;
\ No newline at end of file
diff --git a/vhdl_ls.toml b/vhdl_ls.toml
index d4f78c7..7976b5a 100644
--- a/vhdl_ls.toml
+++ b/vhdl_ls.toml
@@ -2,4 +2,8 @@
 
 top_simple.files = [
     'src/top_simple.vhd'
+    ]
+top_shift.files = [
+    'src/top_shift.vhd'
+    ,'src/t_top_shift.vhd'
     ]
\ No newline at end of file