top_uart solutions

1 files changed, 7 insertions, 1 deletions

diff --git a/src/baudcnt.vhd b/src/baudcnt.vhd
index 4e18aa7..ec46aa5 100644
--- a/src/baudcnt.vhd
+++ b/src/baudcnt.vhd
@@ -1,5 +1,6 @@
 library ieee;
 use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
 
 entity baudcnt is
   port (
@@ -10,7 +11,12 @@ entity baudcnt is
 end entity;
 
 architecture rtl of baudcnt is
+  signal cnt, ncnt : unsigned(9 downto 0);
 begin
-
+  cnt <= (others => '0') when rst_n = '0' else
+         ncnt when rising_edge(clk);
+  ncnt <= to_unsigned(0, cnt'length) when start_i = '1' or cnt = 2 else
+          cnt + 1;
+  en_o <= '1' when cnt = 2 else '0';
 end architecture rtl;