moved edgedetection to edge module, 6 clock design

1 files changed, 5 insertions, 1 deletions

diff --git a/src/edge.vhd b/src/edge.vhd
index 23dba70..d510660 100644
--- a/src/edge.vhd
+++ b/src/edge.vhd
@@ -10,7 +10,11 @@ entity edge is
 end entity;
 
 architecture rtl of edge is
+  signal sr, srnext : std_ulogic_vector(5 downto 0);
 begin
-
+  sr <= "000000" when rst_n = '0' else srnext when rising_edge(clk);
+  srnext(5) <= x_i;
+  srnext(4 downto 0) <= sr(5 downto 1);
+  edge_o <= '1' when sr = "111000" or sr = "000111" else '0';
 end architecture rtl;