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author | Friedrich Beckmann <friedrich.beckmann@hs-augsburg.de> | 2024-03-08 10:14:47 +0100 |
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committer | Friedrich Beckmann <friedrich.beckmann@hs-augsburg.de> | 2024-03-08 10:14:47 +0100 |
commit | 3467ff482ed8a58b525c992329df639872e52fdc (patch) | |
tree | 6b8577919e5dba2244397d04758a9d512d7ab2e8 /src/top_hex.vhd | |
parent | 1b8c2521421c92e7bbaf119ebc95d7bf22f39e10 (diff) |
add top_hex
Diffstat (limited to 'src/top_hex.vhd')
-rw-r--r-- | src/top_hex.vhd | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/src/top_hex.vhd b/src/top_hex.vhd new file mode 100644 index 0000000..cfe2d33 --- /dev/null +++ b/src/top_hex.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity top_hex is +port ( SW : in std_ulogic_vector(9 downto 0); + HEX0 : out std_ulogic_vector(6 downto 0); + HEX1 : out std_ulogic_vector(6 downto 0); + HEX2 : out std_ulogic_vector(6 downto 0); + LEDR : out std_ulogic_vector(9 downto 0)); +end entity; + +architecture rtl of top_hex is +begin + +LEDR <= SW; + +bin2seg_i0: entity work.bin2seg + port map( + bin_i => SW(3 downto 0), + seg_o => HEX0 +); + +HEX1 <= "1111111"; +HEX2 <= "1111111"; + +end architecture rtl; |