top_uart solutions

1 files changed, 26 insertions, 2 deletions

diff --git a/src/top_uart.vhd b/src/top_uart.vhd
index 4cc6c01..d53f06d 100644
--- a/src/top_uart.vhd
+++ b/src/top_uart.vhd
@@ -16,13 +16,37 @@ architecture rtl of top_uart is
   signal clk     : std_ulogic;
   signal rst_n   : std_ulogic;
   signal en, txd : std_ulogic;
+  signal start   : std_ulogic;
 begin
   -- Assign the inputs to signals with reasonable names
   clk <= CLOCK_50;
   rst_n <= KEY(0);
 
-  txd <= '0';
-  en <= '0';
+  edge_inst: entity work.edge
+   port map(
+      clk    => clk,
+      rst_n  => rst_n,
+      x_i    => KEY(1),
+      edge_o => start
+  );
+
+  baudcnt_inst: entity work.baudcnt
+   port map(
+      clk     => clk,
+      rst_n   => rst_n,
+      start_i => start,
+      en_o    => en
+  );
+
+  uart_tx_shift_inst: entity work.uart_tx_shift
+   port map(
+      clk     => clk,
+      rst_n   => rst_n,
+      start_i => start,
+      en_i    => en,
+      d_i     => SW(7 downto 0),
+      tx_o    => txd
+  );
 
   -- Set the outputs;
   EXP(7 downto 4) <= "0000";