uart rx solutionsolutions

1 files changed, 5 insertions, 1 deletions

diff --git a/src/uart_rx_baudcnt.vhd b/src/uart_rx_baudcnt.vhd
index 16a24a9..779567b 100644
--- a/src/uart_rx_baudcnt.vhd
+++ b/src/uart_rx_baudcnt.vhd
@@ -12,6 +12,10 @@ entity uart_rx_baudcnt is
 end entity;
 
 architecture rtl of uart_rx_baudcnt is
+  signal cnt, ncnt : unsigned(9 downto 0);
 begin
-
+  cnt <= "0000000000" when rst_n = '0' else ncnt when rising_edge(clk);
+  ncnt <= "0000000000" when cnt = 867 or sres_i = '1' else cnt + 1;
+  en_f_o <= '1' when cnt = 867 else '0';
+  en_h_o <= '1' when cnt = 867/2 else '0';
 end architecture rtl;