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author | Friedrich Beckmann <friedrich.beckmann@hs-augsburg.de> | 2024-05-27 17:32:24 +0200 |
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committer | Friedrich Beckmann <friedrich.beckmann@hs-augsburg.de> | 2024-05-28 12:31:52 +0200 |
commit | 2caa12d7f849d5bb5aebed5f306f2def408ae8e3 (patch) | |
tree | c41f4e9678f4e7141668856d204176388d85964c /src/uart_rx_bitcnt.vhd | |
parent | 3dd4ccf8e17309ed97e5bdbd8cff6a2855d284fa (diff) |
uart rx solutionsolutions
Diffstat (limited to 'src/uart_rx_bitcnt.vhd')
-rw-r--r-- | src/uart_rx_bitcnt.vhd | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/uart_rx_bitcnt.vhd b/src/uart_rx_bitcnt.vhd index 7aec27a..78e8a1c 100644 --- a/src/uart_rx_bitcnt.vhd +++ b/src/uart_rx_bitcnt.vhd @@ -15,6 +15,15 @@ entity uart_rx_bitcnt is end entity; architecture rtl of uart_rx_bitcnt is + signal cnt, ncnt : unsigned(3 downto 0); begin + cnt <= "0000" when rst_n = '0' else ncnt when rising_edge(clk); + ncnt <= "0001" when edge_i = '1' and cnt = 0 else + cnt + 1 when en_f_i = '1' and cnt > 0 and cnt < 10 else + "0000" when en_h_i = '1' and cnt = 10 else cnt; + + rx_shift_o <= '1' when cnt >= 2 and cnt <= 9 and en_h_i = '1' else '0'; + dv_o <= '1' when cnt = 9 and en_f_i = '1' else '0'; + rx_baudcnt_res_o <= '1' when cnt = 0 else '0'; end architecture rtl; |