top_simple: add LEDG for outputs

1 files changed, 12 insertions, 11 deletions

diff --git a/src/top_simple.vhd b/src/top_simple.vhd
index 808bb47..11143b4 100644
--- a/src/top_simple.vhd
+++ b/src/top_simple.vhd
@@ -2,9 +2,10 @@ library ieee;
 use ieee.std_logic_1164.all;
 
 -- The inputs of this module are the ten switches SW
--- The outputs are connected to the red LEDs LEDR on the board
+-- The outputs are connected to the red and green LEDs on the board
 entity top_simple is 
 port ( SW   : in      std_ulogic_vector(9 downto 0);
+       LEDG : out     std_ulogic_vector(7 downto 0);
        LEDR : out     std_ulogic_vector(9 downto 0));
 end entity top_simple;
 
@@ -12,25 +13,25 @@ architecture rtl of top_simple is
 begin
 -- Signal Assignment - The LEDR outputs are set to the
 -- value of the switch inputs. Switch the switches and see
--- the LEDs go on and off.
+-- the red LEDs go on and off.
 LEDR <= SW;
 
 -- Access one array element
--- LEDR(5) <= SW(0);
+LEDG(0) <= SW(0);
 
 -- Constant for one element
--- LEDR(0) <= '0';
+LEDG(5) <= '1';
 
--- Constant for an array of  4 elements
--- LEDR(3 downto 0) <= "1111";
+-- Constant for an array of 2 elements
+LEDG(7 downto 6) <= "10";
 
--- Access a 5 Bit subarray
--- LEDR(4 downto 0) <= SW(9 downto 5);
+-- Access a 2 Bit subarray
+LEDG(4 downto 3) <= SW(9 downto 8);
 
 -- A simple boolean AND operator equation
--- LEDR(0) <= SW(0) and SW(1);
+LEDG(1) <= SW(0) and SW(1);
 
 -- AND function via conditional signal assignment
--- LEDR(0) <= '1' when SW(1 downto 0) = "00" else '0';
+LEDG(2) <= '1' when SW(1 downto 0) = "11" else '0';
 
-end architecture rtl;
\ No newline at end of file
+end architecture rtl;