first commit with top_simple synthesis

1 files changed, 36 insertions, 0 deletions

diff --git a/src/top_simple.vhd b/src/top_simple.vhd
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+library ieee;
+use ieee.std_logic_1164.all;
+
+-- The inputs of this module are the ten switches SW
+-- The outputs are connected to the red LEDs LEDR on the board
+entity top_simple is 
+port ( SW   : in      std_ulogic_vector(9 downto 0);
+       LEDR : out     std_ulogic_vector(9 downto 0));
+end entity top_simple;
+
+architecture rtl of top_simple is
+begin
+-- Signal Assignment - The LEDR outputs are set to the
+-- value of the switch inputs. Switch the switches and see
+-- the LEDs go on and off.
+LEDR <= SW;
+
+-- Access one array element
+-- LEDR(5) <= SW(0);
+
+-- Constant for one element
+-- LEDR(0) <= '0';
+
+-- Constant for an array of  4 elements
+-- LEDR(3 downto 0) <= "1111";
+
+-- Access a 5 Bit subarray
+-- LEDR(4 downto 0) <= SW(9 downto 5);
+
+-- A simple boolean AND operator equation
+-- LEDR(0) <= SW(0) and SW(1);
+
+-- AND function via conditional signal assignment
+-- LEDR(0) <= '1' when SW(1 downto 0) = "00" else '0';
+
+end architecture rtl;
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