1 files changed, 4 insertions, 1 deletions
diff --git a/src/top_count.vhd b/src/top_count.vhd
index 57c6998..0a84349 100644
--- a/src/top_count.vhd
+++ b/src/top_count.vhd
@@ -16,6 +16,7 @@ architecture rtl of top_count is
   signal rst_n   : std_ulogic;
   signal x       : std_ulogic;
   signal en      : std_ulogic;
+  signal pwm     : std_ulogic;
   signal cnt     : std_ulogic_vector(3 downto 0);
 begin
   -- Assign the inputs to signals with reasonable names
@@ -24,6 +25,8 @@ begin
   x <= KEY(1);
 
   cnt <= "0000";
+  en <= '0';
+  pwm <= '0';
   
   bin2seg_inst: entity work.bin2seg
    port map(
@@ -34,7 +37,7 @@ begin
   -- Set the outputs;
   EXP(7 downto 4) <= cnt;
   EXP(3 downto 0) <= (3 => en,
-          2 => x,
+          2 => pwm,
           1 => rst_n,
           0 => clk);
   LEDR <= SW;