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Diffstat (limited to 'src/top_count.vhd')
| -rw-r--r-- | src/top_count.vhd | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/src/top_count.vhd b/src/top_count.vhd new file mode 100644 index 0000000..57c6998 --- /dev/null +++ b/src/top_count.vhd @@ -0,0 +1,43 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity top_count is +port ( SW : in std_ulogic_vector(9 downto 0); + KEY : in std_ulogic_vector(3 downto 0); + CLOCK_50 : in std_ulogic; + HEX0 : out std_ulogic_vector(6 downto 0); + EXP : out std_ulogic_vector(7 downto 0); + LEDG : out std_ulogic_vector(3 downto 0); + LEDR : out std_ulogic_vector(9 downto 0)); +end entity; + +architecture rtl of top_count is + signal clk : std_ulogic; + signal rst_n : std_ulogic; + signal x : std_ulogic; + signal en : std_ulogic; + signal cnt : std_ulogic_vector(3 downto 0); +begin + -- Assign the inputs to signals with reasonable names + clk <= CLOCK_50; + rst_n <= KEY(0); + x <= KEY(1); + + cnt <= "0000"; + + bin2seg_inst: entity work.bin2seg + port map( + bin_i => cnt, + seg_o => HEX0 + ); + + -- Set the outputs; + EXP(7 downto 4) <= cnt; + EXP(3 downto 0) <= (3 => en, + 2 => x, + 1 => rst_n, + 0 => clk); + LEDR <= SW; + LEDG <= KEY; + +end architecture rtl;
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