diff options
Diffstat (limited to 'src/top_shift.vhd')
| -rw-r--r-- | src/top_shift.vhd | 14 |
1 files changed, 5 insertions, 9 deletions
diff --git a/src/top_shift.vhd b/src/top_shift.vhd index f6036bc..d0c6f44 100644 --- a/src/top_shift.vhd +++ b/src/top_shift.vhd @@ -14,8 +14,8 @@ architecture rtl of top_shift is signal clk : std_ulogic; signal rst_n : std_ulogic; signal x : std_ulogic; - signal sr, srnext : std_ulogic_vector(0 to 1); - signal en : std_ulogic; + signal sr, srnext : std_ulogic_vector(1 downto 0); + signal en : std_ulogic; begin -- Assign the inputs to signals with reasonable names clk <= CLOCK_50; @@ -33,15 +33,11 @@ begin sr <= "00" when rst_n = '0' else srnext when rising_edge(clk); -- Implement the shift register function with next state logic - srnext(0) <= x; - srnext(1) <= sr(0); + srnext(1) <= x; + srnext(0) <= sr(1); -- Compute the output function from the shift register content - en <= sr(0) xor sr(1); - - -------------------------- - -- New code here - -------------------------- + en <= sr(1) xor sr(0); -- Set the outputs; EXP <= (7 downto 4 => '0', |