1 files changed, 41 insertions, 0 deletions
diff --git a/src/uart_rx.vhd b/src/uart_rx.vhd
index 616b181..37d8486 100644
--- a/src/uart_rx.vhd
+++ b/src/uart_rx.vhd
@@ -11,7 +11,48 @@ entity uart_rx is
 end entity;
 
 architecture rtl of uart_rx is
+  signal edge, shift, baud_en_f, baud_en_h, baud_res : std_ulogic;
+  signal uart_rxd_sync : std_ulogic;
 begin
 
+uart_rx_edge_inst: entity work.uart_rx_edge
+ port map(
+    clk => clk,
+    rst_n => rst_n,
+    rxd_i => uart_rxd_i,
+    rxd_o => uart_rxd_sync,
+    edge_o => edge
+);
+
+uart_rx_shift_inst: entity work.uart_rx_shift
+ port map(
+    clk => clk,
+    rst_n => rst_n,
+    shift_i => shift,
+    ser_i => uart_rxd_sync,
+    d_o => rxd_o
+);
+
+uart_rx_baudcnt_inst: entity work.uart_rx_baudcnt
+ port map(
+    clk => clk,
+    rst_n => rst_n,
+    sres_i => baud_res,
+    en_h_o => baud_en_h,
+    en_f_o => baud_en_f
+);
+
+uart_rx_bitcnt_inst: entity work.uart_rx_bitcnt
+ port map(
+    clk => clk,
+    rst_n => rst_n,
+    edge_i => edge,
+    en_h_i => baud_en_h,
+    en_f_i => baud_en_f,
+    rx_baudcnt_res_o => baud_res,
+    rx_shift_o => shift,
+    dv_o => dv_o
+);
+
 end architecture rtl;