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-rw-r--r--src/uart_rx_baudcnt.vhd17
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diff --git a/src/uart_rx_baudcnt.vhd b/src/uart_rx_baudcnt.vhd
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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity uart_rx_baudcnt is
+ port (
+ clk : in std_ulogic;
+ rst_n : in std_ulogic;
+ sres_i : in std_ulogic;
+ en_h_o : out std_ulogic;
+ en_f_o : out std_ulogic);
+end entity;
+
+architecture rtl of uart_rx_baudcnt is
+begin
+
+end architecture rtl;