| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2024-05-28 | add uart_rx_edge | Friedrich Beckmann | |
| 2024-05-27 | uart rx | Friedrich Beckmann | |
| 2024-05-15 | sim/makefile: added synth step to sim | Friedrich Beckmann | |
| The --synth step finds std_ulogic violations with several drivers | |||
| 2024-05-14 | add top_uart | Friedrich Beckmann | |
| 2024-05-10 | add pwm | Friedrich Beckmann | |
| 2024-05-10 | add top_count | Friedrich Beckmann | |
| 2024-04-28 | sim: make the output of the make command more verbose | Friedrich Beckmann | |
| Hans dumped all ghdl output to a logfile to have a short output on the terminal. I prefer to have a more verbose output in case of errors. In addition I fixed a problem when an error occurs during elaboration as the .ghw file is produced also when ghdl exits with an error. Now make will reproduce the error on each call. | |||
| 2024-04-28 | top_shift: add edge.vhd and ringcnt.vhd as empty modules | Friedrich Beckmann | |
| 2024-03-07 | add top_shift and simulation | Friedrich Beckmann | |
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index : beckmanf/dtlab.git | |
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