src/edge.vhd


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library ieee;
use ieee.std_logic_1164.all;

entity edge is
  port (
    clk     : in std_ulogic;
    rst_n   : in std_ulogic;
    x_i     : in std_ulogic;
    edge_o  : out std_ulogic);
end entity;

architecture rtl of edge is
begin

end architecture rtl;