src/edge.vhd


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

library ieee;
use ieee.std_logic_1164.all;

entity edge is
  port (
    clk     : in std_ulogic;
    rst_n   : in std_ulogic;
    x_i     : in std_ulogic;
    edge_o  : out std_ulogic);
end entity;

architecture rtl of edge is
  signal sr, srnext : std_ulogic_vector(5 downto 0);
begin
  sr <= "000000" when rst_n = '0' else srnext when rising_edge(clk);
  srnext(5) <= x_i;
  srnext(4 downto 0) <= sr(5 downto 1);
  edge_o <= '1' when sr = "111000" or sr = "000111" else '0';
end architecture rtl;