src/pwm.vhd


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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity pwm is
  port (
    clk   : in std_ulogic;
    rst_n : in std_ulogic;
    ctrl_i : in std_ulogic_vector(3 downto 0);
    pwm_o  : out std_ulogic);
end entity;

architecture rtl of pwm is
begin

end architecture rtl;