blob: ddf76a1e037dad9df7e0cb5a2826c77544373590 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
|
library ieee;
use ieee.std_logic_1164.all;
entity t_top_shift is
end entity;
architecture beh of t_top_shift is
signal sim_clk : std_ulogic;
signal sim_rst_n : std_ulogic;
signal sim_x : std_ulogic;
signal sim_y : std_ulogic;
signal sim_sw : std_ulogic_vector(9 downto 0);
signal sim_key : std_ulogic_vector(3 downto 0);
signal sim_ledr : std_ulogic_vector(9 downto 0);
signal sim_ledg : std_ulogic_vector(3 downto 0);
signal sim_exp : std_ulogic_vector(7 downto 0);
signal simstop : boolean := false;
begin
-- Stimuli clock generator
clk_p : process
begin
sim_clk <= '0';
wait for 10 ns;
sim_clk <= '1';
wait for 10 ns;
if simstop then
wait;
end if;
end process;
-- Stimuli reset generator
sim_rst_n <= '0', '1' after 55 ns;
-- Stimuli key push
stim_p : process
begin
sim_x <= '0';
wait until rising_edge(sim_rst_n);
for i in 0 to 5 loop
wait until falling_edge(sim_clk);
end loop;
sim_x <= '1';
wait until falling_edge(sim_clk);
wait until falling_edge(sim_clk);
sim_x <= '0';
wait for 200 ns;
simstop <= true;
wait;
end process ;
-- Device under test instantiation
dut : entity work.top_shift
port map(
SW => sim_sw,
KEY => sim_key,
CLOCK_50 => sim_clk,
EXP => sim_exp,
LEDG => sim_ledg,
LEDR => sim_ledr
);
-- Connect stimuli to input signals
sim_key(0) <= sim_rst_n;
sim_key(1) <= sim_x;
sim_key(3 downto 2) <= "00";
sim_sw <= "1010000001";
-- Check the expansion port y output
sim_y <= sim_exp(3);
end architecture beh;
|
