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library ieee;
use ieee.std_logic_1164.all;
entity t_top_uart is
end entity;
architecture beh of t_top_uart is
signal sim_clk : std_ulogic;
signal sim_rst_n : std_ulogic;
signal sim_x : std_ulogic;
signal sim_uart_rxd : std_ulogic;
signal sim_uart_txd : std_ulogic;
signal sim_sw : std_ulogic_vector(9 downto 0);
signal sim_key : std_ulogic_vector(3 downto 0);
signal sim_ledr : std_ulogic_vector(9 downto 0);
signal sim_ledg : std_ulogic_vector(3 downto 0);
signal sim_exp : std_ulogic_vector(7 downto 0);
signal simstop : boolean := false;
begin
-- Stimuli clock generator
clk_p : process
begin
sim_clk <= '0';
wait for 10 ns;
sim_clk <= '1';
wait for 10 ns;
if simstop then
wait;
end if;
end process;
-- Stimuli reset generator
sim_rst_n <= '0', '1' after 55 ns;
-- UART input - not used...
sim_uart_rxd <= '0';
-- Stimuli key push
stim_p : process
begin
sim_x <= '0';
wait until rising_edge(sim_rst_n);
wait for 200 ns;
sim_x <= '1';
wait for 100 ns;
sim_x <= '0';
wait for 600 ns;
simstop <= true;
wait;
end process ;
top_uart_inst: entity work.top_uart
port map(
SW => sim_sw,
KEY => sim_key,
CLOCK_50 => sim_clk,
UART_RXD => sim_uart_rxd,
UART_TXD => sim_uart_txd,
EXP => sim_exp,
LEDG => sim_ledg,
LEDR => sim_ledr
);
-- Connect stimuli to input signals
sim_key(0) <= sim_rst_n;
sim_key(1) <= sim_x;
sim_key(3 downto 2) <= "00";
sim_sw <= "0001000111";
end architecture beh;
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