src/top_simple.vhd


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library ieee;
use ieee.std_logic_1164.all;

-- The inputs of this module are the ten switches SW
-- The outputs are connected to the red and green LEDs on the board
entity top_simple is 
port ( SW   : in      std_ulogic_vector(9 downto 0);
       LEDG : out     std_ulogic_vector(7 downto 0);
       LEDR : out     std_ulogic_vector(9 downto 0));
end entity top_simple;

architecture rtl of top_simple is
begin
-- Signal Assignment - The LEDR outputs are set to the
-- value of the switch inputs. Switch the switches and see
-- the red LEDs go on and off.
LEDR <= SW;

-- Access one array element
LEDG(0) <= SW(0);

-- Constant for one element
LEDG(5) <= '1';

-- Constant for an array of 2 elements
LEDG(7 downto 6) <= "10";

-- Access a 2 Bit subarray
LEDG(4 downto 3) <= SW(9 downto 8);

-- A simple boolean AND operator equation
LEDG(1) <= SW(0) and SW(1);

-- AND function via conditional signal assignment
LEDG(2) <= '1' when SW(1 downto 0) = "11" else '0';

end architecture rtl;