diff options
| author | Friedrich Beckmann <friedrich.beckmann@tha.de> | 2026-11-08 18:14:54 +0100 |
|---|---|---|
| committer | Friedrich Beckmann <friedrich.beckmann@tha.de> | 2026-11-08 18:14:54 +0100 |
| commit | 5129a5a5448012a53cb9ddae1349c2a2c8571339 (patch) | |
| tree | 41d60bbce7fe0de57cdd92b232682831759de1a8 /kicad/fpga_banks_67.kicad_sch | |
| parent | 9e4911662b81bad61183cca74b8c1905f84e60e4 (diff) | |
Schematic (kicad/), one sheet per function as on ULX3S:
- power: TLV62569 bucks for +1V1 / +3V3, AP2112K LDO for +2V5
- usb: USB-C with PTC and TVS, CH347F for JTAG and UART
- fpga_power, fpga_config, fpga_banks_01/23/67: ECP5 LFE5U-25F caBGA256
(pin compatible with the 45F), quad SPI flash, 50 MHz CLOCK_50,
ball assignment as in PINPLAN.md
- ethernet: RTL8211F gigabit PHY, HR911130A RJ45, shield via 1M || 1nF 2kV
- sdram: 32 MB W9825G6KH-6
- hdmi: TMDS from the FPGA (LVCMOS33D), AC coupled, ESD protected
- user_io: SW, KEY (debounced), LEDR, LEDG, HEX0-HEX3 with DE1 names
- gpio: two DE1 compatible 2x20 headers (THDB-ADA on GPIO_0),
Pmod A/B, ESD arrays
- testpoints: bring-up pads, M3 mounting holes
All parts have LCSC numbers, MPN and manufacturer for JLCPCB assembly;
footprints are cross-checked against the EasyEDA data.
Libraries: ECP5 symbols generated from the Lattice pinout CSVs (kipart),
CH347F, RTL8211F, SM410561N symbols, HR911130A symbol and footprint from
KiCad library merge requests, generator scripts in lib/tools/.
Datasheets of all parts except resistors and capacitors in datasheets/
(manufacturer copyright, not covered by the project licenses).
Diffstat (limited to 'kicad/fpga_banks_67.kicad_sch')
| -rw-r--r-- | kicad/fpga_banks_67.kicad_sch | 5217 |
1 files changed, 5217 insertions, 0 deletions
diff --git a/kicad/fpga_banks_67.kicad_sch b/kicad/fpga_banks_67.kicad_sch new file mode 100644 index 0000000..ff22061 --- /dev/null +++ b/kicad/fpga_banks_67.kicad_sch @@ -0,0 +1,5217 @@ +(kicad_sch + (version 20250114) + (generator "eeschema") + (generator_version "9.0") + (uuid "2739c911-c2b3-56bd-a1e3-d5f9ec82fd06") + (paper "A4") + (title_block + (title "eboard - FPGA banks 6 7") + (date "2026-11-08") + (rev "0.1") + (comment 1 "CERN-OHL-S-2.0") + ) + (lib_symbols +(symbol "eboard_fpga:LFE5U-25F-xBG256x" +(property "Reference" "U" + (at -36.83 33.02 0) + (effects + (font + (size 1.27 1.27)) + (justify right) + (hide no))) +(property "Value" "LFE5U-25F-xBG256x" + (at -36.83 30.480000000000004 0) + (effects + (font + (size 1.27 1.27)) + (justify right) + (hide no))) +(property "Footprint" "Package_BGA:BGA-256_14.0x14.0mm_Layout16x16_P0.8mm_Ball0.45mm_Pad0.32mm_NSMD" + (at -36.83 29.845000000000002 0) + (effects + (font + (size 1.27 1.27)) + (justify right) + (hide yes))) +(property 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Ball assignment preliminary (PINPLAN.md): pins may be\nswapped within a bank during layout; the LPF follows the schematic.\nBalls B1 B2 A2 B3 B14 A15 B15 B16 (PLL inputs on the 45F) carry no clocks." + (exclude_from_sim no) + (at 25.4 27.94 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "ab6d93d6-2965-5c39-859b-af79ad267be4") + ) + (global_label "DRAM_CAS_N" + (shape output) + (at 45.72 81.28 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "974bfe93-a5ab-532d-bd58-d490d28854e4") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 45.72 81.28 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "CLOCK_50" + (shape input) + (at 45.72 83.82 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "d6f92d7e-d893-5ea8-8f30-60baa2973ff9") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 45.72 83.82 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