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+ (text "Strap resistors (RTL8211F datasheet 7.8): PHY address 1, 2 ns TXC and RXC delay inside the PHY,\nRGMII I/O at 3.3 V from DVDD_RG (CFG_EXT = 1, CFG_LDO = 00), LED1/LED2 active high."
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+ (text "ENET_RST_N: 10k pull-down keeps the PHY in reset\nuntil the FPGA drives it high (>= 10 ms low,\nwait 50 ms before MDIO access)."
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+ (text "1.0 V core (DVDD10 pin 21, AVDD10 pins 3, 8, 38): only for the PHY.\nInductor Isat > 600 mA, X5R/X7R capacitors."
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