diff options
Diffstat (limited to 'kicad/fpga_config.kicad_sch')
| -rw-r--r-- | kicad/fpga_config.kicad_sch | 8941 |
1 files changed, 8941 insertions, 0 deletions
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"4c075b7b-eefe-58bc-b3b3-a7e3c15420c6") + ) + (wire + (pts + (xy 236.22 40.64) (xy 236.22 45.72) + ) + (stroke + (width 0) + (type default) + ) + (uuid "8fc650c9-35e8-52ac-87f7-d725c9268154") + ) + (text "Pull-ups to VCCIO8 (TN-02038 Table 6.2).\nFLASH_CS and FLASH_CLK pull-ups next to the flash." + (exclude_from_sim no) + (at 129.54 55.88 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "d4d26640-648a-5362-9bb9-a60db1f4792d") + ) + (text "MCLK series R close to the FPGA ball N9" + (exclude_from_sim no) + (at 147.32 35.56 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "33746bfa-d981-57f7-abdc-5edb9f536b37") + ) + (text "Bank 8 (VCCIO8 = 3.3 V): SPI flash; the other bank 8 I/O drive LEDG[5:0]\nand HEX3[6:5] (they may toggle during configuration)." + (exclude_from_sim no) + (at 45.72 139.7 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "0a8e2aba-0678-571c-a6b2-13d0fe31addf") + ) + (text "PROG button" + (exclude_from_sim no) + (at 45.72 163.83 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "f1ab4dfc-a84d-5685-9c24-116091d6749f") + ) + (text "DONE LED" + (exclude_from_sim no) + (at 63.5 154.94 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "61638a51-1c10-5526-aaec-cf1a9e287d54") + ) + (text "50 MHz system clock (as on the DE1). Goes to a PCLK pin, not to\nB1 B2 A2 B3 B14 A15 B15 B16 (PLL inputs only on the 45F)." + (exclude_from_sim no) + (at 137.16 135.89 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "c006b40b-f529-59af-a31a-c3c46ee7c07e") + ) + (text "FPGA configuration" + (exclude_from_sim no) + (at 25.4 20.32 0) + (effects + (font + (size 2.54 2.54) + (bold yes) + ) + (justify left top) + ) + (uuid "081a7b90-8784-54a4-87b4-6a7f30547c3d") + ) + (text "Test pads (bring-up)" + (exclude_from_sim no) + (at 200.66 27.94 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "7e768703-e1e4-5411-a513-6dbcea392f3a") + ) + (text "Boot: master SPI (MSPI), CFG[2:0] = 010, quad SPI capable; JTAG always available (CH347).\nPROG button reloads the flash, DONE LED lights when the FPGA is configured." + (exclude_from_sim no) + (at 25.4 27.94 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "caee63a5-4c80-5182-b86a-f152566fd23c") + ) + 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