removed sim/pwm and pnr/de1_pwm

4 files changed, 0 insertions, 198 deletions

diff --git a/pnr/de1_pwm/de1_pwm_pins.tcl b/pnr/de1_pwm/de1_pwm_pins.tcl
deleted file mode 100644
index 1d79959..0000000
--- a/pnr/de1_pwm/de1_pwm_pins.tcl
+++ /dev/null
@@ -1,27 +0,0 @@
-# assign pin locations to a quartus project

-

-#----------------------------------------------------------------------

-# Pin Assignments

-set_location_assignment PIN_L1 -to CLOCK_50

-set_location_assignment PIN_R22 -to KEY[0]

-set_location_assignment PIN_R21 -to KEY[1]

-set_location_assignment PIN_L22 -to SW[0]

-set_location_assignment PIN_L21 -to SW[1]

-set_location_assignment PIN_M22 -to SW[2]

-set_location_assignment PIN_V12 -to SW[3]

-set_location_assignment PIN_W12 -to SW[4]

-set_location_assignment PIN_U12 -to SW[5]

-set_location_assignment PIN_U11 -to SW[6]

-set_location_assignment PIN_M2 -to SW[7]

-set_location_assignment PIN_R20 -to LEDR[0]

-set_location_assignment PIN_R19 -to LEDR[1]

-set_location_assignment PIN_U19 -to LEDR[2]

-set_location_assignment PIN_Y19 -to LEDR[3]

-set_location_assignment PIN_T18 -to LEDR[4]

-set_location_assignment PIN_V19 -to LEDR[5]

-set_location_assignment PIN_Y18 -to LEDR[6]

-set_location_assignment PIN_U18 -to LEDR[7]

-set_location_assignment PIN_H12 -to GPO_1[0]

-set_location_assignment PIN_H13 -to GPO_1[1]

-set_location_assignment PIN_H14 -to GPO_1[2]

-# ----------------------------------------------------------------------------

diff --git a/pnr/de1_pwm/makefile b/pnr/de1_pwm/makefile
deleted file mode 100644
index 5ed5024..0000000
--- a/pnr/de1_pwm/makefile
+++ /dev/null
@@ -1,87 +0,0 @@
-## ----------------------------------------------------------------------------

-## Script     : makefile

-## ----------------------------------------------------------------------------

-## Author     : Johann Faerber, Friedrich Beckmann

-## Company    : University of Applied Sciences Augsburg

-## ----------------------------------------------------------------------------

-## Description: This makefile allows automating design flow with Quartus,

-##              it is based on a design directory structure described in 

-##              ../makefile

-## ----------------------------------------------------------------------------

-

-###################################################################

-# Project Configuration: 

-#

-# - assign variable SIM_PROJECT_NAME with the top level project name

-# - add additional VHDL sources to SOURCE_FILES, if necessary

-#

-# Prerequisite: 

-#   - mandatory design directory structure (see end of file)

-#   - assumes file name of top level entity de1_$(PROJECT)_structure.vhd

-###################################################################

-

-SIM_PROJECT_NAME = pwm

-PROJECT = de1_$(SIM_PROJECT_NAME)

-

-# Prototype Board FPGA family and device settings

-# DE1

-FAMILY = "Cyclone II"

-DEVICE = EP2C20F484C7

-PROGFILEEXT = sof

-# DEMMK

-# FAMILY = "MAX II"

-# DEVICE = EPM2210F324C3

-# PROGFILEEXT = pof

-# DE2

-#FAMILY = "Cyclone II"

-#DEVICE = EP2C35F484C7

-#PROGFILEEXT = sof

-# DE0

-#FAMILY = "Cyclone IV E"

-#DEVICE = EP4CE22F17C6

-#PROGFILEEXT = sof

-

-# Here the VHDL files for synthesis are defined. 

-include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources

-

-# Add the toplevel fpga vhdl file

-SOURCE_FILES = $(SYN_SOURCE_FILES) \

-../../src/$(PROJECT)_structure.vhd

-

-include ../makefile

-

-## ----------------------------------------------------------------------------

-## Description: 

-## ------------

-## assumes the following design directory structure as prerequisite

-## 

-## DigitaltechnikPraktikum

-## |   

-## +---src

-## |       and2gate_equation.vhd

-## |       invgate_equation.vhd

-## |       mux2to1_structure.vhd

-## |       or2gate_equation.vhd

-## |       t_mux2to1.vhd

-## |       de1_mux2to1_structure.vhd

-## |

-## +---sim

-## |   |   makefile

-## |   |

-## |   \---mux2to1

-## |           makefile

-## |           makefile.sources

-## |

-## +---pnr

-## |   |   makefile

-## |   |

-## |   \---de1_mux2to1

-## |           de1_mux2to1_pins.tcl

-## |           makefile

-## |

-## \---scripts

-##         de1_pin_assignments_minimumio.csv

-##         de1_pin_assignments_minimumio.tcl

-##         modelsim.ini

-##         quartus_project_settings.tcl

-## ----------------------------------------------------------------------------

diff --git a/sim/pwm/makefile b/sim/pwm/makefile
deleted file mode 100644
index 962c45a..0000000
--- a/sim/pwm/makefile
+++ /dev/null
@@ -1,67 +0,0 @@
-## ----------------------------------------------------------------------------
-## Script     : makefile
-## ----------------------------------------------------------------------------
-## Author     : Johann Faerber, Friedrich Beckmann
-## Company    : University of Applied Sciences Augsburg
-## ----------------------------------------------------------------------------
-## Description: This makefile allows automating design flow with ModelSim,
-##              it is based on a design directory structure described in 
-##              ../makefile
-## ----------------------------------------------------------------------------
-
-###################################################################
-# Project Configuration: 
-#
-# assign variable PROJECT with the top level project name
-#
-# Prerequisite: 
-#   - mandatory design directory structure (see end of file)
-#   - assumes file name of testbench t_$(PROJECT).vhd
-###################################################################
-
-PROJECT = pwm
-
-include ./makefile.sources
-
-# Add here the testbench file
-SOURCE_FILES = $(SYN_SOURCE_FILES) \
-../../src/t_$(PROJECT).vhd
-
-include ../makefile
-
-## ----------------------------------------------------------------------------
-## Description: 
-## ------------
-## assumes the following design directory structure as prerequisite
-## 
-## DigitaltechnikPraktikum
-## |   
-## +---src
-## |       and2gate_equation.vhd
-## |       invgate_equation.vhd
-## |       mux2to1_structure.vhd
-## |       or2gate_equation.vhd
-## |       t_mux2to1.vhd
-## |       de1_mux2to1_structure.vhd
-## |
-## +---sim
-## |   |   makefile
-## |   |
-## |   \---mux2to1
-## |           makefile
-## |           makefile.sources
-## |
-## +---pnr
-## |   |   makefile
-## |   |
-## |   \---de1_mux2to1
-## |           de1_mux2to1_pins.tcl
-## |           makefile
-## |
-## \---scripts
-##         de1_pin_assignments_minimumio.csv
-##         de1_pin_assignments_minimumio.tcl
-##         modelsim.ini
-##         quartus_project_settings.tcl
-## ----------------------------------------------------------------------------
-
diff --git a/sim/pwm/makefile.sources b/sim/pwm/makefile.sources
deleted file mode 100644
index 5db2028..0000000
--- a/sim/pwm/makefile.sources
+++ /dev/null
@@ -1,17 +0,0 @@
-## ----------------------------------------------------------------------------
-## Script     : makefile.sources
-## ----------------------------------------------------------------------------
-## Author     : Johann Faerber
-## Company    : University of Applied Sciences Augsburg
-## ----------------------------------------------------------------------------
-## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES
-##              Attention !!!
-##              -------------
-##              Do not forget a new line after the final source file !
-## ----------------------------------------------------------------------------
-
-SYN_SOURCE_FILES = \
-../../src/pwm_rtl.vhd \
-
-# do not delete this line
-# -----------------------------------------------------------------------------