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authorJohann Faerber <johann.faerber@hs-augsburg.de>2022-03-09 09:18:57 +0100
committerJohann Faerber <johann.faerber@hs-augsburg.de>2022-03-09 09:18:57 +0100
commitfd7c3d6c1352353f3ee2da9267308a51fd67315d (patch)
tree2736826f00cb225fd56618324a2611e1441b57d3
parent1aaff2bfc0a6b96b2d1215a6576685fff9f56b2a (diff)
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+# Ignore files for git
+
+# Emacs backup files
+*~
+*.bak
+.emacs-vhdl-cache*
+
+# ModelSim working library
+work
+
+# Quartus internal database
+db
+incremental_db
+
+
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-# 2022 VLSI Lab Problems
-
-VLSI Design Module - Laboratory Exercises \ No newline at end of file
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+VHDL Essentials
+===============
+
+Part of the VLSI Design Module this project repository contains design data and documents of
+laboratory exercises.
+
+It addresses the topics
+
+* Hardware Description Language VHDL
+* VLSI Design Toolchain
+* Design Collaboration using Version Control System
+* Documentation
+
+The DE1-Prototype Board serves as a platform for rapid prototyping of digital systems:
+
+![DE1 Prototype Board ](doc/images/de1-prototypeboard.png){width=50%}
+
+
+
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