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authorJohann Faerber <johann.faerber@hs-augsburg.de>2022-03-13 15:14:37 +0100
committerJohann Faerber <johann.faerber@hs-augsburg.de>2022-03-13 15:14:37 +0100
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-VHDL Essentials
+VLSI Design - Laboratory Exercises
===============
Part of the VLSI Design Module this project repository contains design data and documents of