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| author | Johann Faerber <johann.faerber@hs-augsburg.de> | 2022-03-13 15:36:10 +0100 |
|---|---|---|
| committer | Johann Faerber <johann.faerber@hs-augsburg.de> | 2022-03-13 15:36:10 +0100 |
| commit | de2f6cd37b8906f63bc5e007339aa40fc409ba2f (patch) | |
| tree | fe0e2b03cf9796d98d3e808545de72844ce1266e /sim/binto7segment/makefile.sources | |
| parent | f48e8a6dce1613cba40e3e94d02b00875e8297d2 (diff) | |
added sim/binto7segment
Diffstat (limited to 'sim/binto7segment/makefile.sources')
| -rw-r--r-- | sim/binto7segment/makefile.sources | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/sim/binto7segment/makefile.sources b/sim/binto7segment/makefile.sources new file mode 100644 index 0000000..0b73c93 --- /dev/null +++ b/sim/binto7segment/makefile.sources @@ -0,0 +1,17 @@ +## ----------------------------------------------------------------------------
+## Script : makefile.sources
+## ----------------------------------------------------------------------------
+## Author : Johann Faerber
+## Company : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES
+## Attention !!!
+## -------------
+## Do not forget a new line after the final source file !
+## ----------------------------------------------------------------------------
+
+SYN_SOURCE_FILES = \
+../../src/binto7segment_truthtable.vhd \
+
+# do not delete this line
+# -----------------------------------------------------------------------------
\ No newline at end of file |