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| author | Friedrich Beckmann <friedrich.beckmann@hs-augsburg.de> | 2023-03-15 22:30:08 +0100 |
|---|---|---|
| committer | Friedrich Beckmann <friedrich.beckmann@hs-augsburg.de> | 2023-03-15 22:30:08 +0100 |
| commit | df418208aa0570a99f6ab6657d54ee65d6162168 (patch) | |
| tree | c68b3f968866e978852eed508a5605e914be3951 /sim/de1_sine/makefile | |
| parent | 0ace43acf8c1953289ae9ae3756d9f10949f060e (diff) | |
added de1_sine sinewave generator for ADC/DAC board
I added a sinewave generator based on DDS in VHDL to
generate a sinewave with the ADC/DAC board. This can
be used to demonstrate the Aliasing Lowpass filter.
Diffstat (limited to 'sim/de1_sine/makefile')
| -rw-r--r-- | sim/de1_sine/makefile | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/sim/de1_sine/makefile b/sim/de1_sine/makefile new file mode 100644 index 0000000..e662da8 --- /dev/null +++ b/sim/de1_sine/makefile @@ -0,0 +1,8 @@ +PROJECT = de1_sine + +include ./makefile.sources + +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/t_$(PROJECT).vhd + +include ../makefile |