1 files changed, 17 insertions, 0 deletions
diff --git a/sim/binto7segment/makefile.sources b/sim/binto7segment/makefile.sources
new file mode 100644
index 0000000..0b73c93
--- /dev/null
+++ b/sim/binto7segment/makefile.sources
@@ -0,0 +1,17 @@
+## ----------------------------------------------------------------------------
+## Script     : makefile.sources
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES
+##              Attention !!!
+##              -------------
+##              Do not forget a new line after the final source file !
+## ----------------------------------------------------------------------------
+
+SYN_SOURCE_FILES = \
+../../src/binto7segment_truthtable.vhd \
+
+# do not delete this line
+# -----------------------------------------------------------------------------
+\ No newline at end of file