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+## ----------------------------------------------------------------------------
+## Script : makefile.sources
+## ----------------------------------------------------------------------------
+## Author : Johann Faerber
+## Company : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES
+## Attention !!!
+## -------------
+## Do not forget a new line after the final source file !
+## ----------------------------------------------------------------------------
+
+SYN_SOURCE_FILES = \
+../../src/d_ff_rtl.vhd \
+../../src/e_falling_edge_detector.vhd \
+../../src/a_falling_edge_detector_structure.vhd \
+
+# do not delete this line
+# -----------------------------------------------------------------------------