2 files changed, 0 insertions, 84 deletions
diff --git a/sim/pwm/makefile b/sim/pwm/makefile
deleted file mode 100644
index 962c45a..0000000
--- a/sim/pwm/makefile
+++ /dev/null
@@ -1,67 +0,0 @@
-## ----------------------------------------------------------------------------
-## Script     : makefile
-## ----------------------------------------------------------------------------
-## Author     : Johann Faerber, Friedrich Beckmann
-## Company    : University of Applied Sciences Augsburg
-## ----------------------------------------------------------------------------
-## Description: This makefile allows automating design flow with ModelSim,
-##              it is based on a design directory structure described in 
-##              ../makefile
-## ----------------------------------------------------------------------------
-
-###################################################################
-# Project Configuration: 
-#
-# assign variable PROJECT with the top level project name
-#
-# Prerequisite: 
-#   - mandatory design directory structure (see end of file)
-#   - assumes file name of testbench t_$(PROJECT).vhd
-###################################################################
-
-PROJECT = pwm
-
-include ./makefile.sources
-
-# Add here the testbench file
-SOURCE_FILES = $(SYN_SOURCE_FILES) \
-../../src/t_$(PROJECT).vhd
-
-include ../makefile
-
-## ----------------------------------------------------------------------------
-## Description: 
-## ------------
-## assumes the following design directory structure as prerequisite
-## 
-## DigitaltechnikPraktikum
-## |   
-## +---src
-## |       and2gate_equation.vhd
-## |       invgate_equation.vhd
-## |       mux2to1_structure.vhd
-## |       or2gate_equation.vhd
-## |       t_mux2to1.vhd
-## |       de1_mux2to1_structure.vhd
-## |
-## +---sim
-## |   |   makefile
-## |   |
-## |   \---mux2to1
-## |           makefile
-## |           makefile.sources
-## |
-## +---pnr
-## |   |   makefile
-## |   |
-## |   \---de1_mux2to1
-## |           de1_mux2to1_pins.tcl
-## |           makefile
-## |
-## \---scripts
-##         de1_pin_assignments_minimumio.csv
-##         de1_pin_assignments_minimumio.tcl
-##         modelsim.ini
-##         quartus_project_settings.tcl
-## ----------------------------------------------------------------------------
-
diff --git a/sim/pwm/makefile.sources b/sim/pwm/makefile.sources
deleted file mode 100644
index 5db2028..0000000
--- a/sim/pwm/makefile.sources
+++ /dev/null
@@ -1,17 +0,0 @@
-## ----------------------------------------------------------------------------
-## Script     : makefile.sources
-## ----------------------------------------------------------------------------
-## Author     : Johann Faerber
-## Company    : University of Applied Sciences Augsburg
-## ----------------------------------------------------------------------------
-## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES
-##              Attention !!!
-##              -------------
-##              Do not forget a new line after the final source file !
-## ----------------------------------------------------------------------------
-
-SYN_SOURCE_FILES = \
-../../src/pwm_rtl.vhd \
-
-# do not delete this line
-# -----------------------------------------------------------------------------