diff options
Diffstat (limited to 'src/de1_adc_rtl.vhd')
| -rw-r--r-- | src/de1_adc_rtl.vhd | 51 |
1 files changed, 1 insertions, 50 deletions
diff --git a/src/de1_adc_rtl.vhd b/src/de1_adc_rtl.vhd index d82c892..ec18462 100644 --- a/src/de1_adc_rtl.vhd +++ b/src/de1_adc_rtl.vhd @@ -2,10 +2,6 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; --- PLL for 100 MHz speed -library altera_mf; -use altera_mf.all; - entity de1_adc is port ( CLOCK_50 : in std_ulogic; SW : in std_ulogic_vector(9 downto 0); @@ -31,57 +27,12 @@ end entity; architecture rtl of de1_adc is - -- Altera PLL - component altpll - generic ( - clk0_divide_by : natural; - clk0_duty_cycle : natural; - clk0_multiply_by : natural; --- clk0_phase_shift : STRING; --- compensate_clock : STRING; - inclk0_input_frequency : natural; --- intended_device_family : STRING; --- lpm_hint : STRING; --- lpm_type : STRING; - operation_mode : string; - port_inclk0 : string; - port_clk0 : string - ); - port ( - clk : out std_logic_vector (5 downto 0); - inclk : in std_logic_vector (1 downto 0) - ); - end component; - - signal pll_inclk : std_logic_vector(1 downto 0); - signal pll_outclk : std_logic_vector(5 downto 0); - signal clk,rst_n : std_ulogic; signal dac_a_dat, dac_b_dat, adc_a_dat, adc_b_dat : std_ulogic_vector(13 downto 0); begin - pll_i0 : altpll - generic map ( - clk0_divide_by => 10, - clk0_duty_cycle => 50, - clk0_multiply_by => 13, --- clk0_phase_shift => "0", --- compensate_clock => "CLK0", - inclk0_input_frequency => 20000, - operation_mode => "NORMAL", - port_inclk0 => "PORT_USED", - port_clk0 => "PORT_USED" - ) - port map ( - inclk => pll_inclk, - clk => pll_outclk - ); - - pll_inclk(0) <= CLOCK_50; - pll_inclk(1) <= '0'; - clk <= pll_outclk(0); - --clk <= CLOCK_50; + clk <= CLOCK_50; rst_n <= KEY0; LEDR <= "00000000" & ADC_OTR_A & ADC_OTR_B when rising_edge(clk); |