1 files changed, 56 insertions, 0 deletions
diff --git a/src/sine_rtl.vhd b/src/sine_rtl.vhd
new file mode 100644
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--- /dev/null
+++ b/src/sine_rtl.vhd
@@ -0,0 +1,56 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+entity sine is
+  port (clk         : in  std_ulogic;
+        rst_n       : in  std_ulogic;
+        phase_inc_i : in  std_ulogic_vector(9 downto 0);
+        phase_o     : out std_ulogic_vector(9 downto 0);
+        sample_o    : out std_ulogic_vector(13 downto 0));
+end entity;
+
+architecture rtl of sine is
+
+  signal phase : unsigned(9 downto 0);
+
+  type rom_t is array (0 to 1023) of signed(13 downto 0);
+
+  function sine_rom_init_f return rom_t is
+    variable phase_real : real := 0.0;
+    variable sinereal : real;
+    variable sinequan : signed(13 downto 0);
+    variable rom_v : rom_t;
+  begin
+    for i in 0 to 1023 loop
+      phase_real := 2.0 * MATH_PI * real(i) / 1024.0;
+      sinereal := sin(phase_real);
+      sinequan := to_signed(integer(sinereal * real(2**13-1)), 14);
+      rom_v (i) := sinequan;
+    end loop;
+    return rom_v;
+  end function;
+
+  constant rom : rom_t := sine_rom_init_f;
+
+  signal rom_out_reg : signed(13 downto 0);
+  signal rom_index_reg  : integer range 0 to 1023;
+  
+begin
+
+  -- phase accumulator
+  phase <= "0000000000" when rst_n = '0' else
+           phase + unsigned(phase_inc_i) when rising_edge(clk);
+  
+  rom_index_reg <= to_integer(phase) when rising_edge(clk);
+
+  rom_out_reg <= rom(rom_index_reg) when rising_edge(clk);
+  
+  sample_o <= "00000000000000" when rst_n = '0' else
+    std_ulogic_vector(rom_out_reg) when rising_edge(clk);
+
+  phase_o <= "0000000000" when rst_n = '0' else
+    std_ulogic_vector(phase) when rising_edge(clk);
+
+end architecture rtl;