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diff --git a/src/t_de1_sta.vhd b/src/t_de1_sta.vhd
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+--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg
+--
+--   Licensed under the Apache License, Version 2.0 (the "License");
+--   you may not use this file except in compliance with the License.
+--   You may obtain a copy of the License at
+--
+--       http://www.apache.org/licenses/LICENSE-2.0
+--
+--   Unless required by applicable law or agreed to in writing, software
+--   distributed under the License is distributed on an "AS IS" BASIS,
+--   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--   See the License for the specific language governing permissions and
+--   limitations under the License.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+entity t_de1_sta is
+end;
+
+architecture tbench of t_de1_sta is
+
+  component de1_sta is
+    port (
+      CLOCK_50    : in    std_ulogic;
+      KEY0        : in    std_ulogic;
+      LEDR        : out   std_ulogic_vector(9 downto 0)
+      );
+  end component;
+
+  signal clk, reset_n     : std_ulogic;
+  signal ledr             : std_ulogic_vector(9 downto 0);
+  signal key0             : std_ulogic;
+
+  signal simrun : boolean := true;
+
+begin
+
+  de1_sta_i0 : de1_sta
+    port map (
+      CLOCK_50    => clk,
+      KEY0        => reset_n,
+      LEDR        => ledr);
+
+  clock_p : process
+  begin
+    clk <= '0';
+    wait for 10 ns;
+    clk <= '1';
+    wait for 10 ns;
+    if not simrun then
+      wait;
+    end if;
+  end process clock_p;
+
+  simrun <= false after 5 ms;
+
+  reset_p : process
+  begin
+    reset_n <= '0';
+    wait for 10 ns;
+    reset_n <= '1';
+    wait;
+  end process reset_p;
+
+
+end;  -- architecture