diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/de1_and2gate_structure.vhd | 50 | ||||
| -rw-r--r-- | src/t_and2gate.vhd | 75 |
2 files changed, 125 insertions, 0 deletions
diff --git a/src/de1_and2gate_structure.vhd b/src/de1_and2gate_structure.vhd new file mode 100644 index 0000000..fcab62a --- /dev/null +++ b/src/de1_and2gate_structure.vhd @@ -0,0 +1,50 @@ +------------------------------------------------------------------------------- +-- Module : de1_and2gate +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: test the module and2gate on a DE1 prototype board +-- connecting device under test (DUT) and2gate +-- to input/output signals of the DE1 prototype board +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY de1_and2gate IS + PORT ( + SW : IN std_ulogic_vector(1 DOWNTO 0); -- Toggle Switch[2:0] + LEDR : OUT std_ulogic_vector(2 DOWNTO 0) -- LED Red[2:0] + ); +END de1_and2gate; + +ARCHITECTURE structure OF de1_and2gate IS + + COMPONENT and2gate IS + PORT ( + a_i : IN std_ulogic; + b_i : IN std_ulogic; + y_o : OUT std_ulogic); + END COMPONENT and2gate; + +BEGIN + + -- assigning input signals to LEDs + LEDR(0) <= SW(0); + LEDR(1) <= SW(1); + + -- connecting device under test with peripheral elements + DUT : and2gate + PORT MAP ( + a_i => SW(0), + b_i => SW(1), + y_o => LEDR(2)); + +END structure; +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- diff --git a/src/t_and2gate.vhd b/src/t_and2gate.vhd new file mode 100644 index 0000000..e0cdec2 --- /dev/null +++ b/src/t_and2gate.vhd @@ -0,0 +1,75 @@ +------------------------------------------------------------------------------- +-- Module : t_and2gate +------------------------------------------------------------------------------- +-- Author : <haf@fh-augsburg.de> +-- Company : University of Applied Sciences Augsburg +-- Copyright (c) 2011 <haf@fh-augsburg.de> +------------------------------------------------------------------------------- +-- Description: Testbench for design "and2gate" +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +------------------------------------------------------------------------------- + +ENTITY t_and2gate IS +END t_and2gate; + +------------------------------------------------------------------------------- + +ARCHITECTURE tbench OF t_and2gate IS + + COMPONENT and2gate IS + PORT ( + a_i : IN std_ulogic; + b_i : IN std_ulogic; + y_o : OUT std_ulogic); + END COMPONENT and2gate; + + -- definition of a clock period + CONSTANT period : time := 10 ns; + + -- component ports + SIGNAL a_i : std_ulogic; + SIGNAL b_i : std_ulogic; + SIGNAL y_o : std_ulogic; + +BEGIN -- tbench + + -- component instantiation + MUV : and2gate + PORT MAP ( + a_i => a_i, + b_i => b_i, + y_o => y_o); + + stimuli_p : PROCESS + + BEGIN + a_i <= '0'; -- set a value to input a_i + b_i <= '0'; -- set a value to input b_i + WAIT FOR period; -- values are assigned here + + a_i <= '1'; -- change value of a_i + WAIT FOR period; + + a_i <= '0'; -- change value of a_i + b_i <= '1'; -- change value of b_i + WAIT FOR period; + + a_i <= '1'; -- change value of a_i + WAIT FOR period; + + WAIT; + END PROCESS; + +END tbench; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- |