blob: 117c3f191552ea26397f175f5bfea2027f8e1f3f (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
|
-------------------------------------------------------------------------------
-- Module : rtl
-------------------------------------------------------------------------------
-- Author : Johann Faerber
-- Company : University of Applied Sciences Augsburg
-------------------------------------------------------------------------------
-- Description: detects a falling edge of input signal x_i
-- and produces a high-active signal for one clock period at
-- output fall_o
-- clk_i __|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|
-- x_i -----|___________________________________|-----------
-- fall_o ________|-----|______________________________________
--
-- rtl model based on two flip flops with output logic
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ARCHITECTURE rtl OF falling_edge_detector IS
SIGNAL q0, q1 : std_ulogic; -- D-Type Flip-Flop outputs
BEGIN
dflipflop_0 : q0 <= '0' WHEN (rst_ni = '0') ELSE
x_i WHEN rising_edge(clk_i);
dflipflop_1 : q1 <= '0' WHEN (rst_ni = '0') ELSE
q0 WHEN rising_edge(clk_i);
output_logic : fall_o <= ; -- fill in the correct equation here
END rtl;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
|
