blob: af06a3e61323a6bcd4ae958607dab93ee8621b9d (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
|
-------------------------------------------------------------------------------
-- Module : d_ff
-------------------------------------------------------------------------------
-- Author : Johann Faerber
-- Company : University of Applied Sciences Augsburg
-------------------------------------------------------------------------------
-- Description: D-Type Flip-Flop
-- including a low-active asynchronous reset input rst_ni
-- and a high-active enable input en_pi
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY d_ff IS
PORT (
clk_i : IN std_ulogic;
rst_ni : IN std_ulogic;
d_i : IN std_ulogic;
q_o : OUT std_ulogic
);
END d_ff;
ARCHITECTURE rtl OF d_ff IS
BEGIN
dflipflop_p : q_o <= '0' WHEN (rst_ni = '0') ELSE
d_i WHEN rising_edge(clk_i);
END rtl;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
|
