blob: b75c3b5e2bf1fa67db547c73542036b5d4505718 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
|
-------------------------------------------------------------------------------
-- Module : de1_fir
-------------------------------------------------------------------------------
-- Author : Matthias Kamuf
-- Company : University of Applied Sciences Augsburg
-------------------------------------------------------------------------------
-- Description: Top-level of module de1_fir
--
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY de1_fir IS
PORT (
CLOCK_50 : IN std_ulogic;
KEY0 : IN std_ulogic;
DAC_MODE : OUT std_ulogic;
DAC_WRT_A : OUT std_ulogic;
DAC_WRT_B : OUT std_ulogic;
DAC_CLK_A : OUT std_ulogic;
DAC_CLK_B : OUT std_ulogic;
DAC_DA : OUT std_ulogic_vector(13 DOWNTO 0);
DAC_DB : OUT std_ulogic_vector(13 DOWNTO 0);
POWER_ON : OUT std_ulogic;
ADC_CLK_A : OUT std_ulogic;
ADC_CLK_B : OUT std_ulogic;
ADC_OEB_A : OUT std_ulogic;
ADC_OEB_B : OUT std_ulogic;
ADC_DA : IN std_ulogic_vector(13 DOWNTO 0);
ADC_DB : IN std_ulogic_vector(13 DOWNTO 0);
ADC_OTR_A : IN std_ulogic;
ADC_OTR_B : IN std_ulogic;
LEDR : OUT std_ulogic_vector(9 DOWNTO 0));
END de1_fir;
ARCHITECTURE structure OF de1_fir IS
COMPONENT fir IS
PORT (
clk_i : IN std_ulogic;
rst_ni : IN std_ulogic;
valid_i : IN std_ulogic;
sample_i : IN std_ulogic_vector(13 DOWNTO 0);
valid_o : OUT std_ulogic;
sample_o : OUT std_ulogic_vector(13 DOWNTO 0));
END COMPONENT fir;
-- component ports
SIGNAL clk : std_ulogic;
SIGNAL rst_n : std_ulogic;
SIGNAL adc_a_dat, adc_b_dat : std_ulogic_vector(13 DOWNTO 0);
BEGIN
filter : fir
PORT MAP (
clk_i => clk,
rst_ni => rst_n,
valid_i => ,
sample_i => ,
valid_o => ,
sample_o => );
-- clock and reset signal
clk <= CLOCK_50;
rst_n <= KEY0;
-- valid and overflow indicator
LEDR <= valid & ADC_OTR_B & ADC_OTR_A & "0000000";
-- DAC in dual port mode
DAC_MODE <= '1';
DAC_WRT_A <= clk;
DAC_WRT_B <= clk;
DAC_CLK_A <= clk;
DAC_CLK_B <= clk;
-- DAC on board has 00000000000000 as minimum value
-- and 11111111111111 as maximum value
-- therefore the conversion has to look like this
-- input signed value output DAC value
-- minimum 10000000000000 00000000000000
-- zero 00000000000000 10000000000000
-- maximum 01111111111111 11111111111111
-- assign to DAC channels
DAC_DA <= "10000000000000" WHEN rst_n = '0' ELSE adc_a_dat WHEN falling_edge(clk);
DAC_DB <= "10000000000000" WHEN rst_n = '0' ELSE adc_b_dat WHEN falling_edge(clk);
-- ADC section
ADC_CLK_A <= clk;
ADC_CLK_B <= clk;
ADC_OEB_A <= '0';
ADC_OEB_B <= '0';
adc_a_dat <= (OTHERS => '0') WHEN rst_n = '0' ELSE ADC_DA WHEN rising_edge(clk);
adc_b_dat <= (OTHERS => '0') WHEN rst_n = '0' ELSE ADC_DB WHEN rising_edge(clk);
-- switch on DAC/ADC
POWER_ON <= '1';
END structure;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
|
