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-------------------------------------------------------------------------------
-- Module : fir_mac
-------------------------------------------------------------------------------
-- Author : Matthias Kamuf
-- Company : University of Applied Sciences Augsburg
-------------------------------------------------------------------------------
-- Description: Module fir_mac used as part of fir
--
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY fir_mac IS
GENERIC (
gen_w_in : natural := 14;
gen_w_c : natural := 12);
PORT (
clk_i : IN std_ulogic;
rst_ni : IN std_ulogic;
hl_i : IN std_ulogic_vector(gen_w_c-1 DOWNTO 0); -- left coefficient
hr_i : IN std_ulogic_vector(gen_w_c-1 DOWNTO 0); -- right coefficient
d_i : IN std_ulogic_vector(gen_w_in-1 DOWNTO 0); -- data input first register
d_o : OUT std_ulogic_vector(gen_w_in-1 DOWNTO 0); -- data output second register
sum_o : OUT std_ulogic_vector(gen_w_in+gen_w_c DOWNTO 0)); -- registered output sum_o
END fir_mac;
ARCHITECTURE rtl OF fir_mac IS
BEGIN
-- shift register at sample rate
-- products left and right of first register
-- output sum (registered) at sample rate
END rtl;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
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