1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
|
-------------------------------------------------------------------------------
-- Module : fir
-------------------------------------------------------------------------------
-- Author : Matthias Kamuf
-- Company : University of Applied Sciences Augsburg
-------------------------------------------------------------------------------
-- Description: Top-level of module fir
--
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY fir IS
PORT (
clk_i : IN std_ulogic;
rst_ni : IN std_ulogic;
valid_i : IN std_ulogic;
sample_i : IN std_ulogic_vector(13 DOWNTO 0);
valid_o : OUT std_ulogic;
sample_o : OUT std_ulogic_vector(13 DOWNTO 0));
END fir;
ARCHITECTURE structure OF fir IS
-- coefficient wordlength
CONSTANT W_C : natural := 12;
-- type definition for coefficients
TYPE COEFFS_TYPE IS ARRAY (0 TO 7) OF integer;
-- HERE SHALL BE THE CONTENT OF hqi.txt --->
-- <---
COMPONENT fir_mac IS
GENERIC (
gen_w_in : natural := 14;
gen_w_c : natural := 12);
PORT (
clk_i : IN std_ulogic;
rst_ni : IN std_ulogic;
hl_i : IN std_ulogic_vector(gen_w_c-1 DOWNTO 0); -- left coefficient
hr_i : IN std_ulogic_vector(gen_w_c-1 DOWNTO 0); -- right coefficient
d_i : IN std_ulogic_vector(gen_w_in-1 DOWNTO 0); -- data input first register
d_o : OUT std_ulogic_vector(gen_w_in-1 DOWNTO 0); -- data output second register
sum_o : OUT std_ulogic_vector(gen_w_in+gen_w_c DOWNTO 0)); -- registered output sum_o
END COMPONENT fir_mac;
-- dynamic range of sum given coefficients above
CONSTANT W_DYN : natural := 1;
BEGIN
-- component instantiation
mac0 : fir_mac
GENERIC MAP (
gen_w_in => sample_i'length,
gen_w_c => W_C)
PORT MAP (
clk_i => clk_i,
rst_ni => rst_ni,
hl_i => ,
hr_i => ,
d_i => ,
d_o => ,
sum_o => );
mac1 : fir_mac
GENERIC MAP (
gen_w_in => sample_i'length,
gen_w_c => W_C)
PORT MAP (
clk_i => clk_i,
rst_ni => rst_ni,
hl_i => ,
hr_i => ,
d_i => ,
d_o => ,
sum_o => );
mac2 : fir_mac
GENERIC MAP (
gen_w_in => sample_i'length,
gen_w_c => W_C)
PORT MAP (
clk_i => clk_i,
rst_ni => rst_ni,
hl_i => ,
hr_i => ,
d_i => ,
d_o => ,
sum_o => );
mac3 : fir_mac
GENERIC MAP (
gen_w_in => sample_i'length,
gen_w_c => W_C)
PORT MAP (
clk_i => clk_i,
rst_ni => rst_ni,
hl_i => ,
hr_i => ,
d_i => ,
d_o => ,
sum_o => );
-- combining sums of individual fir_mac
-- final sum
-- truncated final sum (registered) at sample rate
-- (registered and delayed due to pipeline stage in fir_mac) valid signal at sample rate
END structure;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
|
