blob: 42888c63d01becefbc43425fafc7b5c835aa5a4b (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
|
-------------------------------------------------------------------------------
-- Module : t_cntdn
-------------------------------------------------------------------------------
-- Author : <haf@fh-augsburg.de>
-- Company : University of Applied Sciences Augsburg
-- Copyright (c) 2011 <haf@fh-augsburg.de>
-------------------------------------------------------------------------------
-- Description: Testbench for design "cntdn"
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY t_cntdn IS
END t_cntdn;
ARCHITECTURE tbench OF t_cntdn IS
COMPONENT cntdn
PORT (
clk_i : IN std_ulogic;
rst_ni : IN std_ulogic;
en_pi : IN std_ulogic;
count_o : OUT std_ulogic_vector(3 DOWNTO 0);
tc_o : OUT std_ulogic);
END COMPONENT;
-- definition of a clock period
CONSTANT period : time := 10 ns;
-- switch for clock generator
SIGNAL clken_p : boolean := true;
-- component ports
SIGNAL clk_i : std_ulogic;
SIGNAL rst_ni : std_ulogic;
SIGNAL en_pi : std_ulogic;
SIGNAL count_o : std_ulogic_vector(3 DOWNTO 0);
SIGNAL tc_o : std_ulogic;
BEGIN -- tbench
-- component instantiation
DUT : cntdn
PORT MAP (
clk_i => clk_i,
rst_ni => rst_ni,
en_pi => en_pi,
count_o => count_o,
tc_o => tc_o);
-- clock generation
clock_proc : PROCESS
BEGIN
WHILE clken_p LOOP
clk_i <= '0'; WAIT FOR period/2;
clk_i <= '1'; WAIT FOR period/2;
END LOOP;
WAIT;
END PROCESS;
-- initial reset, always necessary at the beginning of a simulation
-- initial reset, always necessary at the beginning of a simulation
-----------------------------------------------------------------------------
-- Following a verification plan:
-- ------------------------------
-- 1. t = 0 ns: activate asynchronous reset
-- 2. t = 10 ns: deactivate asynchronous reset
-----------------------------------------------------------------------------
reset : rst_ni <= '0', '1' AFTER period;
stimuli_p : PROCESS
BEGIN
---------------------------------------------------------------------------
-- ... continuing with the verification plan:
---------------------------------------------------------------------------
WAIT UNTIL rising_edge(rst_ni); -- wait for reset
-- ... is deactivated
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- 2. activate enable
-- 3. Wait for a full counting cycle
---------------------------------------------------------------------------
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- 4. After another five periods: Deactivate Enable
---------------------------------------------------------------------------
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- 5. After another three periods: Activate Enable
-- 6. Simulate another complete counting cycle
---------------------------------------------------------------------------
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- 7. Simulate until tc_o = 1 again
---------------------------------------------------------------------------
---------------------------------------------------------------------------
clken_p <= false; -- switch clock generator off
WAIT; -- suspend proces
END PROCESS;
END tbench;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
|
