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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity t_de1_sine is
end entity;
architecture beh of t_de1_sine is
component de1_sine is
port (
CLOCK_50 : in std_ulogic;
KEY0 : in std_ulogic;
SW : in std_ulogic_vector(9 downto 0);
DAC_MODE : out std_ulogic;
DAC_WRT_A : out std_ulogic;
DAC_WRT_B : out std_ulogic;
DAC_CLK_A : out std_ulogic;
DAC_CLK_B : out std_ulogic;
DAC_DA : out std_ulogic_vector(13 downto 0);
DAC_DB : out std_ulogic_vector(13 downto 0);
POWER_ON : out std_ulogic;
ADC_CLK_A : out std_ulogic;
ADC_CLK_B : out std_ulogic;
ADC_OEB_A : out std_ulogic;
ADC_OEB_B : out std_ulogic;
LEDR : out std_ulogic_vector(9 downto 0));
end component;
signal clk : std_ulogic;
signal rst_n : std_ulogic;
signal dac_mode, dac_wrt_a, dac_wrt_b, dac_clk_a,
dac_clk_b, power_on, adc_clk_a, adc_clk_b,
adc_oeb_a, adc_oeb_b : std_ulogic;
signal dac_da, dac_db : std_ulogic_vector(13 downto 0);
signal ledr, sw : std_ulogic_vector(9 downto 0);
signal simstop : boolean;
begin
dut : de1_sine
port map(
CLOCK_50 => clk,
KEY0 => rst_n,
SW => sw,
DAC_MODE => dac_mode,
DAC_WRT_A => dac_wrt_a,
DAC_WRT_B => dac_wrt_b,
DAC_CLK_A => dac_clk_a,
DAC_CLK_B => dac_clk_b,
DAC_DA => dac_da,
DAC_DB => dac_db,
POWER_ON => power_on,
ADC_CLK_A => adc_clk_a,
ADC_CLK_B => adc_clk_b,
ADC_OEB_A => adc_oeb_a,
ADC_OEB_B => adc_oeb_b,
LEDR => ledr
);
clk_p : process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
if simstop then
wait;
end if;
end process;
rst_n <= '0', '1' after 50 ns;
simstop <= false, true after 30 us;
sw <= "0000000001";
end architecture;
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