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authorFriedrich Beckmann <friedrich.beckmann@tha.de>2026-03-28 15:51:26 +0100
committerFriedrich Beckmann <friedrich.beckmann@tha.de>2026-03-28 15:51:26 +0100
commit61f71ec79f5f326b86d2dc73a1b880d454dca36e (patch)
tree12d99c99c2c6cc4505769b4ee5cb1a7b737a7e0b /top_count/src/counter.scala
parentb60a75cf4e8d6660e38bf15d9257c342c2d1aa97 (diff)
add top_countHEADmaster
Diffstat (limited to 'top_count/src/counter.scala')
-rw-r--r--top_count/src/counter.scala19
1 files changed, 19 insertions, 0 deletions
diff --git a/top_count/src/counter.scala b/top_count/src/counter.scala
new file mode 100644
index 0000000..d8dc06e
--- /dev/null
+++ b/top_count/src/counter.scala
@@ -0,0 +1,19 @@
+package top_count
+
+import spinal.core._
+
+case class counter() extends Component {
+ val io = new Bundle {
+ val en_i = in Bool()
+ val cnt_o = out UInt(4 bits)
+ }
+
+ // The counter register
+ val cnt = Reg(UInt(4 bits)) init 0
+
+ when (io.en_i) {
+ cnt := cnt + 1
+ }
+ // Map the register content to the output
+ io.cnt_o := cnt
+}