2 files changed, 43 insertions, 0 deletions
diff --git a/top_simple/src/Config.scala b/top_simple/src/Config.scala
new file mode 100644
index 0000000..dbfe54b
--- /dev/null
+++ b/top_simple/src/Config.scala
@@ -0,0 +1,16 @@
+package top_simple
+
+import spinal.core._
+import spinal.core.sim._
+
+object Config {
+  def spinal = SpinalConfig(
+    targetDirectory = "top_simple/gen",
+    defaultConfigForClockDomains = ClockDomainConfig(
+      resetActiveLevel = HIGH
+    ),
+    onlyStdLogicVectorAtTopLevelIo = false
+  )
+
+  def sim = SimConfig.withGhdl.withConfig(spinal).withFstWave
+}
diff --git a/top_simple/src/top_simple.scala b/top_simple/src/top_simple.scala
new file mode 100644
index 0000000..ec43fe8
--- /dev/null
+++ b/top_simple/src/top_simple.scala
@@ -0,0 +1,27 @@
+package top_simple
+
+import spinal.core._
+
+// Hardware definition
+case class top_simple() extends Component {
+  val io = new Bundle {
+    val SW = in  Bits(10 bits)
+    val LEDR = out  Bits(10 bits)
+    val LEDG  = out Bits(8 bits)
+  }
+  // Remove io_ from the port names in generated vhdl code
+  noIoPrefix()
+
+  io.LEDR := io.SW
+  io.LEDG := "00000000"
+
+}
+
+// The following defines the vhdl and verilog code generation
+object verilog extends App {
+  Config.spinal.generateVerilog(top_simple())
+}
+
+object vhdl extends App {
+  Config.spinal.generateVhdl(top_simple())
+}