aboutsummaryrefslogtreecommitdiff
path: root/top_simple/src/Config.scala
blob: 682d4631325e927dfdfdf74b56342b51bdca16f0 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
package top_simple

import spinal.core._
import spinal.core.sim._

object Config {
  def spinal = SpinalConfig(
    targetDirectory = sys.props.getOrElse("spinalTargetDir", "top_simple/gen"),
    defaultConfigForClockDomains = ClockDomainConfig(
      resetActiveLevel = HIGH
    ),
    onlyStdLogicVectorAtTopLevelIo = false
  )

  def sim = SimConfig.withGhdl.withConfig(spinal).withFstWave
}