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Diffstat (limited to 'VexRiscv/scripts/Murax')
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diff --git a/VexRiscv/scripts/Murax/arty_a7/README.md b/VexRiscv/scripts/Murax/arty_a7/README.md new file mode 100644 index 0000000..ad781f3 --- /dev/null +++ b/VexRiscv/scripts/Murax/arty_a7/README.md @@ -0,0 +1,129 @@ +This example is for the Digilent ARTY A7 35T board. + +# Using the example + +## Before Starting + +You should make sure you have the following tools installed: + * vivado 2018.1 or later + * riscv toolchain (riscv64-unknown-elf) + * sbt + +## Board setup +Make sure you have a rev E board. If you have a later version check that the +flash part is S25FL128SAGMF100. + +Jumper settings for board rev E: + * Disconnect anything from the connectors (Pmod, Arduino) + * Jumpers: JP1 and JP2 on, others off. + +## Building + +You should be able to just type `make` and get output similar to this; +``` +... +Memory region Used Size Region Size %age Used + RAM: 896 B 2 KB 43.75% +... +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1457.785 ; gain = 243.430 ; free physical = 17940 ; free virtual = 57159 +--------------------------------------------------------------------------------- +... +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:02:42 ; elapsed = 00:02:58 . Memory (MB): peak = 1986.879 ; gain = 772.523 ; free physical = 17454 ; free virtual = 56670 +--------------------------------------------------------------------------------- +... +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:02:45 ; elapsed = 00:03:01 . Memory (MB): peak = 1986.879 ; gain = 772.523 ; free physical = 17457 ; free virtual = 56673 +--------------------------------------------------------------------------------- +... +Writing bitstream ./toplevel.bit... +... +mmi files generated +... +******************************************** + ./soc_latest_sw.bit correctly generated +******************************************** +... +******************************************** + ./soc_latest_sw.mcs correctly generated +******************************************** + +INFO: [Common 17-206] Exiting Vivado at Thu Nov 28 04:00:50 2019... +``` + +The process should take around 8 minutes on a reasonably fast computer. + +## Programming + +### Direct FPGA RAM programming + +Run `make prog` to program the bit file directly to FPGA RAM. + +You should get output like the following; +``` +... +****** Xilinx hw_server v2018.1 + **** Build date : Apr 4 2018-18:56:09 + ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. + +INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210319AB569AA +INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. +WARNING: [Labtools 27-3361] The debug hub core was not detected. +Resolution: +1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active. +2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'. +For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908). +INFO: [Labtools 27-3164] End of startup status: HIGH +INFO: [Common 17-206] Exiting Vivado at Thu Nov 28 04:01:36 2019... +``` + +After programming the LED4~LED7 shall show some activity. + +### QSPI flash programming + +Run `make flash` to program the bit file to the QSPI flash. + +You should get output like the following; +``` +... +****** Xilinx hw_server v2018.1 + **** Build date : Apr 4 2018-18:56:09 + ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. + + +INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210319AB569AA +INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. +... +INFO: [Labtools 27-3164] End of startup status: HIGH +Mfg ID : 1 Memory Type : 20 Memory Capacity : 18 Device ID 1 : 0 Device ID 2 : 0 +Performing Erase Operation... +Erase Operation successful. +Performing Program and Verify Operations... +Program/Verify Operation successful. +INFO: [Labtoolstcl 44-377] Flash programming completed successfully +program_hw_cfgmem: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:52 . Memory (MB): peak = 1792.711 ; gain = 8.000 ; free physical = 17712 ; free virtual = 56943 +INFO: [Labtoolstcl 44-464] Closing hw_target localhost:3121/xilinx_tcf/Digilent/210319AB569AA +... +INFO: [Common 17-206] Exiting Vivado at Thu Nov 28 04:06:28 2019... +``` + +After programming the flash you need to press the "PROG" button on the board. Then after a second or so the "DONE" LED shall be ON and LED4~LED7 shall show some activity. + + +## Connect + +After programming you should be able to connect to the serial port and have some output. + +On Linux you can do this using a command like `screen /dev/ttyUSB1`. Other good alternatives: + +* moserial (GUI) +* picocom (can be launched via the file "picocom_arty") + +Parameters: +* port is : /dev/ttyUSB1 +* flowcontrol : none +* baudrate is : 115200 +* parity is : none +* databits are : 8 +* stopbits are : 1 diff --git a/VexRiscv/scripts/Murax/arty_a7/arty_a7.xdc b/VexRiscv/scripts/Murax/arty_a7/arty_a7.xdc new file mode 100644 index 0000000..5ddd8fe --- /dev/null +++ b/VexRiscv/scripts/Murax/arty_a7/arty_a7.xdc @@ -0,0 +1,366 @@ +set_property PACKAGE_PIN F4 [get_ports tck] +set_property IOSTANDARD LVCMOS33 [get_ports tck] + +set_property PACKAGE_PIN D2 [get_ports tms] +set_property IOSTANDARD LVCMOS33 [get_ports tms] + +set_property PACKAGE_PIN D4 [get_ports tdo] +set_property IOSTANDARD LVCMOS33 [get_ports tdo] +set_property PULLUP true [get_ports tdo] + +set_property PACKAGE_PIN E2 [get_ports tdi] +set_property IOSTANDARD LVCMOS33 [get_ports tdi] + +set_property PACKAGE_PIN D3 [get_ports trst] +set_property IOSTANDARD LVCMOS33 [get_ports trst] +set_property PULLUP true [get_ports trst] + + +## serial:0.tx +set_property PACKAGE_PIN D10 [get_ports serial_tx] +set_property IOSTANDARD LVCMOS33 [get_ports serial_tx] +## serial:0.rx +set_property PACKAGE_PIN A9 [get_ports serial_rx] +set_property IOSTANDARD LVCMOS33 [get_ports serial_rx] +## clk100:0 +set_property PACKAGE_PIN E3 [get_ports clk100] +set_property IOSTANDARD LVCMOS33 [get_ports clk100] +## cpu_reset:0 +set_property PACKAGE_PIN C2 [get_ports cpu_reset] +set_property IOSTANDARD LVCMOS33 [get_ports cpu_reset] +## eth_ref_clk:0 +#set_property LOC G18 [get_ports eth_ref_clk] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_ref_clk] +## user_led:0 +set_property PACKAGE_PIN H5 [get_ports user_led0] +set_property IOSTANDARD LVCMOS33 [get_ports user_led0] +## user_led:1 +set_property PACKAGE_PIN J5 [get_ports user_led1] +set_property IOSTANDARD LVCMOS33 [get_ports user_led1] +## user_led:2 +set_property PACKAGE_PIN T9 [get_ports user_led2] +set_property IOSTANDARD LVCMOS33 [get_ports user_led2] +## user_led:3 +set_property PACKAGE_PIN T10 [get_ports user_led3] +set_property IOSTANDARD LVCMOS33 [get_ports user_led3] +## user_sw:0 +set_property PACKAGE_PIN A8 [get_ports user_sw0] +set_property IOSTANDARD LVCMOS33 [get_ports user_sw0] +## user_sw:1 +set_property PACKAGE_PIN C11 [get_ports user_sw1] +set_property IOSTANDARD LVCMOS33 [get_ports user_sw1] +## user_sw:2 +set_property PACKAGE_PIN C10 [get_ports user_sw2] +set_property IOSTANDARD LVCMOS33 [get_ports user_sw2] +## user_sw:3 +set_property PACKAGE_PIN A10 [get_ports user_sw3] +set_property IOSTANDARD LVCMOS33 [get_ports user_sw3] +## user_btn:0 +set_property PACKAGE_PIN D9 [get_ports user_btn0] +set_property IOSTANDARD LVCMOS33 [get_ports user_btn0] +## user_btn:1 +set_property PACKAGE_PIN C9 [get_ports user_btn1] +set_property IOSTANDARD LVCMOS33 [get_ports user_btn1] +## user_btn:2 +set_property PACKAGE_PIN B9 [get_ports user_btn2] +set_property IOSTANDARD LVCMOS33 [get_ports user_btn2] +## user_btn:3 +set_property PACKAGE_PIN B8 [get_ports user_btn3] +set_property IOSTANDARD LVCMOS33 [get_ports user_btn3] +## spiflash_1x:0.cs_n +#set_property LOC L13 [get_ports spiflash_1x_cs_n] +#set_property IOSTANDARD LVCMOS33 [get_ports spiflash_1x_cs_n] +# ## spiflash_1x:0.mosi +#set_property LOC K17 [get_ports spiflash_1x_mosi] +#set_property IOSTANDARD LVCMOS33 [get_ports spiflash_1x_mosi] +# ## spiflash_1x:0.miso +#set_property LOC K18 [get_ports spiflash_1x_miso] +#set_property IOSTANDARD LVCMOS33 [get_ports spiflash_1x_miso] +# ## spiflash_1x:0.wp +#set_property LOC L14 [get_ports spiflash_1x_wp] +#set_property IOSTANDARD LVCMOS33 [get_ports spiflash_1x_wp] +# ## spiflash_1x:0.hold +#set_property LOC M14 [get_ports spiflash_1x_hold] +#set_property IOSTANDARD LVCMOS33 [get_ports spiflash_1x_hold] +# ## ddram:0.a +#set_property LOC R2 [get_ports ddram_a[0]] +#set_property SLEW FAST [get_ports ddram_a[0]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_a[0]] +# ## ddram:0.a +#set_property LOC M6 [get_ports ddram_a[1]] +#set_property SLEW FAST [get_ports ddram_a[1]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_a[1]] +# ## ddram:0.a +#set_property LOC N4 [get_ports ddram_a[2]] +#set_property SLEW FAST [get_ports ddram_a[2]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_a[2]] +# ## ddram:0.a +#set_property LOC T1 [get_ports ddram_a[3]] +#set_property SLEW FAST [get_ports ddram_a[3]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_a[3]] +# ## ddram:0.a +#set_property LOC N6 [get_ports ddram_a[4]] +#set_property SLEW FAST [get_ports ddram_a[4]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_a[4]] +# ## ddram:0.a +#set_property LOC R7 [get_ports ddram_a[5]] +#set_property SLEW FAST [get_ports ddram_a[5]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_a[5]] +# ## ddram:0.a +#set_property LOC V6 [get_ports ddram_a[6]] +#set_property SLEW FAST [get_ports ddram_a[6]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_a[6]] +# ## ddram:0.a +#set_property LOC U7 [get_ports ddram_a[7]] +#set_property SLEW FAST [get_ports ddram_a[7]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_a[7]] +# ## ddram:0.a +#set_property LOC R8 [get_ports ddram_a[8]] +#set_property SLEW FAST [get_ports ddram_a[8]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_a[8]] +# ## ddram:0.a +#set_property LOC V7 [get_ports ddram_a[9]] +#set_property SLEW FAST [get_ports ddram_a[9]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_a[9]] +# ## ddram:0.a +#set_property LOC R6 [get_ports ddram_a[10]] +#set_property SLEW FAST [get_ports ddram_a[10]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_a[10]] +# ## ddram:0.a +#set_property LOC U6 [get_ports ddram_a[11]] +#set_property SLEW FAST [get_ports ddram_a[11]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_a[11]] +# ## ddram:0.a +#set_property LOC T6 [get_ports ddram_a[12]] +#set_property SLEW FAST [get_ports ddram_a[12]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_a[12]] +# ## ddram:0.a +#set_property LOC T8 [get_ports ddram_a[13]] +#set_property SLEW FAST [get_ports ddram_a[13]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_a[13]] +# ## ddram:0.ba +#set_property LOC R1 [get_ports ddram_ba[0]] +#set_property SLEW FAST [get_ports ddram_ba[0]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_ba[0]] +# ## ddram:0.ba +#set_property LOC P4 [get_ports ddram_ba[1]] +#set_property SLEW FAST [get_ports ddram_ba[1]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_ba[1]] +# ## ddram:0.ba +#set_property LOC P2 [get_ports ddram_ba[2]] +#set_property SLEW FAST [get_ports ddram_ba[2]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_ba[2]] +# ## ddram:0.ras_n +#set_property LOC P3 [get_ports ddram_ras_n] +#set_property SLEW FAST [get_ports ddram_ras_n] +#set_property IOSTANDARD SSTL15 [get_ports ddram_ras_n] +# ## ddram:0.cas_n +#set_property LOC M4 [get_ports ddram_cas_n] +#set_property SLEW FAST [get_ports ddram_cas_n] +#set_property IOSTANDARD SSTL15 [get_ports ddram_cas_n] +# ## ddram:0.we_n +#set_property LOC P5 [get_ports ddram_we_n] +#set_property SLEW FAST [get_ports ddram_we_n] +#set_property IOSTANDARD SSTL15 [get_ports ddram_we_n] +# ## ddram:0.cs_n +#set_property LOC U8 [get_ports ddram_cs_n] +#set_property SLEW FAST [get_ports ddram_cs_n] +#set_property IOSTANDARD SSTL15 [get_ports ddram_cs_n] +# ## ddram:0.dm +#set_property LOC L1 [get_ports ddram_dm[0]] +#set_property SLEW FAST [get_ports ddram_dm[0]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_dm[0]] +# ## ddram:0.dm +#set_property LOC U1 [get_ports ddram_dm[1]] +#set_property SLEW FAST [get_ports ddram_dm[1]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_dm[1]] +# ## ddram:0.dq +#set_property LOC K5 [get_ports ddram_dq[0]] +#set_property SLEW FAST [get_ports ddram_dq[0]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[0]] +#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[0]] +# ## ddram:0.dq +#set_property LOC L3 [get_ports ddram_dq[1]] +#set_property SLEW FAST [get_ports ddram_dq[1]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[1]] +#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[1]] +# ## ddram:0.dq +#set_property LOC K3 [get_ports ddram_dq[2]] +#set_property SLEW FAST [get_ports ddram_dq[2]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[2]] +#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[2]] +# ## ddram:0.dq +#set_property LOC L6 [get_ports ddram_dq[3]] +#set_property SLEW FAST [get_ports ddram_dq[3]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[3]] +#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[3]] +# ## ddram:0.dq +#set_property LOC M3 [get_ports ddram_dq[4]] +#set_property SLEW FAST [get_ports ddram_dq[4]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[4]] +#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[4]] +# ## ddram:0.dq +#set_property LOC M1 [get_ports ddram_dq[5]] +#set_property SLEW FAST [get_ports ddram_dq[5]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[5]] +#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[5]] +# ## ddram:0.dq +#set_property LOC L4 [get_ports ddram_dq[6]] +#set_property SLEW FAST [get_ports ddram_dq[6]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[6]] +#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[6]] +# ## ddram:0.dq +#set_property LOC M2 [get_ports ddram_dq[7]] +#set_property SLEW FAST [get_ports ddram_dq[7]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[7]] +#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[7]] +# ## ddram:0.dq +#set_property LOC V4 [get_ports ddram_dq[8]] +#set_property SLEW FAST [get_ports ddram_dq[8]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[8]] +#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[8]] +# ## ddram:0.dq +#set_property LOC T5 [get_ports ddram_dq[9]] +#set_property SLEW FAST [get_ports ddram_dq[9]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[9]] +#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[9]] +# ## ddram:0.dq +#set_property LOC U4 [get_ports ddram_dq[10]] +#set_property SLEW FAST [get_ports ddram_dq[10]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[10]] +#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[10]] +# ## ddram:0.dq +#set_property LOC V5 [get_ports ddram_dq[11]] +#set_property SLEW FAST [get_ports ddram_dq[11]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[11]] +#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[11]] +# ## ddram:0.dq +#set_property LOC V1 [get_ports ddram_dq[12]] +#set_property SLEW FAST [get_ports ddram_dq[12]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[12]] +#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[12]] +# ## ddram:0.dq +#set_property LOC T3 [get_ports ddram_dq[13]] +#set_property SLEW FAST [get_ports ddram_dq[13]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[13]] +#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[13]] +# ## ddram:0.dq +#set_property LOC U3 [get_ports ddram_dq[14]] +#set_property SLEW FAST [get_ports ddram_dq[14]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[14]] +#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[14]] +# ## ddram:0.dq +#set_property LOC R3 [get_ports ddram_dq[15]] +#set_property SLEW FAST [get_ports ddram_dq[15]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[15]] +#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[15]] +# ## ddram:0.dqs_p +#set_property LOC N2 [get_ports ddram_dqs_p[0]] +#set_property SLEW FAST [get_ports ddram_dqs_p[0]] +#set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_dqs_p[0]] +# ## ddram:0.dqs_p +#set_property LOC U2 [get_ports ddram_dqs_p[1]] +#set_property SLEW FAST [get_ports ddram_dqs_p[1]] +#set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_dqs_p[1]] +# ## ddram:0.dqs_n +#set_property LOC N1 [get_ports ddram_dqs_n[0]] +#set_property SLEW FAST [get_ports ddram_dqs_n[0]] +#set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_dqs_n[0]] +# ## ddram:0.dqs_n +#set_property LOC V2 [get_ports ddram_dqs_n[1]] +#set_property SLEW FAST [get_ports ddram_dqs_n[1]] +#set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_dqs_n[1]] +# ## ddram:0.clk_p +#set_property LOC U9 [get_ports ddram_clk_p] +#set_property SLEW FAST [get_ports ddram_clk_p] +#set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_clk_p] +# ## ddram:0.clk_n +#set_property LOC V9 [get_ports ddram_clk_n] +#set_property SLEW FAST [get_ports ddram_clk_n] +#set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_clk_n] +# ## ddram:0.cke +#set_property LOC N5 [get_ports ddram_cke] +#set_property SLEW FAST [get_ports ddram_cke] +#set_property IOSTANDARD SSTL15 [get_ports ddram_cke] +# ## ddram:0.odt +#set_property LOC R5 [get_ports ddram_odt] +#set_property SLEW FAST [get_ports ddram_odt] +#set_property IOSTANDARD SSTL15 [get_ports ddram_odt] +# ## ddram:0.reset_n +#set_property LOC K6 [get_ports ddram_reset_n] +#set_property SLEW FAST [get_ports ddram_reset_n] +#set_property IOSTANDARD SSTL15 [get_ports ddram_reset_n] +# ## eth_clocks:0.tx +#set_property LOC H16 [get_ports eth_clocks_tx] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_clocks_tx] +# ## eth_clocks:0.rx +#set_property LOC F15 [get_ports eth_clocks_rx] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_clocks_rx] +# ## eth:0.rst_n +#set_property LOC C16 [get_ports eth_rst_n] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_rst_n] +# ## eth:0.mdio +#set_property LOC K13 [get_ports eth_mdio] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_mdio] +# ## eth:0.mdc +#set_property LOC F16 [get_ports eth_mdc] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_mdc] +# ## eth:0.rx_dv +#set_property LOC G16 [get_ports eth_rx_dv] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_dv] +# ## eth:0.rx_er +#set_property LOC C17 [get_ports eth_rx_er] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_er] +# ## eth:0.rx_data +#set_property LOC D18 [get_ports eth_rx_data[0]] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_data[0]] +# ## eth:0.rx_data +#set_property LOC E17 [get_ports eth_rx_data[1]] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_data[1]] +# ## eth:0.rx_data +#set_property LOC E18 [get_ports eth_rx_data[2]] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_data[2]] +# ## eth:0.rx_data +#set_property LOC G17 [get_ports eth_rx_data[3]] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_data[3]] +# ## eth:0.tx_en +#set_property LOC H15 [get_ports eth_tx_en] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_en] +# ## eth:0.tx_data +#set_property LOC H14 [get_ports eth_tx_data[0]] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_data[0]] +# ## eth:0.tx_data +#set_property LOC J14 [get_ports eth_tx_data[1]] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_data[1]] +# ## eth:0.tx_data +#set_property LOC J13 [get_ports eth_tx_data[2]] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_data[2]] +# ## eth:0.tx_data +#set_property LOC H17 [get_ports eth_tx_data[3]] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_data[3]] +# ## eth:0.col +#set_property LOC D17 [get_ports eth_col] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_col] +# ## eth:0.crs +#set_property LOC G14 [get_ports eth_crs] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_crs] + +set_property INTERNAL_VREF 0.75 [get_iobanks 34] + + +create_clock -period 10.000 -name clk100 [get_nets clk100] + +#create_clock -name eth_rx_clk -period 40.0 [get_nets eth_rx_clk] + +#create_clock -name eth_tx_clk -period 40.0 [get_nets eth_tx_clk] + +#set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_rx_clk]] -asynchronous + +#set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_tx_clk]] -asynchronous + +#set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets eth_rx_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_tx_clk]] -asynchronous + + + + +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] diff --git a/VexRiscv/scripts/Murax/arty_a7/arty_a7_org.xdc b/VexRiscv/scripts/Murax/arty_a7/arty_a7_org.xdc new file mode 100644 index 0000000..75c81b1 --- /dev/null +++ b/VexRiscv/scripts/Murax/arty_a7/arty_a7_org.xdc @@ -0,0 +1,350 @@ + ## serial:0.tx +set_property LOC D10 [get_ports serial_tx] +set_property IOSTANDARD LVCMOS33 [get_ports serial_tx] + ## serial:0.rx +set_property LOC A9 [get_ports serial_rx] +set_property IOSTANDARD LVCMOS33 [get_ports serial_rx] + ## clk100:0 +set_property LOC E3 [get_ports clk100] +set_property IOSTANDARD LVCMOS33 [get_ports clk100] + ## cpu_reset:0 +set_property LOC C2 [get_ports cpu_reset] +set_property IOSTANDARD LVCMOS33 [get_ports cpu_reset] + ## eth_ref_clk:0 +#set_property LOC G18 [get_ports eth_ref_clk] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_ref_clk] + ## user_led:0 +set_property LOC H5 [get_ports user_led0] +set_property IOSTANDARD LVCMOS33 [get_ports user_led0] + ## user_led:1 +set_property LOC J5 [get_ports user_led1] +set_property IOSTANDARD LVCMOS33 [get_ports user_led1] + ## user_led:2 +set_property LOC T9 [get_ports user_led2] +set_property IOSTANDARD LVCMOS33 [get_ports user_led2] + ## user_led:3 +set_property LOC T10 [get_ports user_led3] +set_property IOSTANDARD LVCMOS33 [get_ports user_led3] + ## user_sw:0 +set_property LOC A8 [get_ports user_sw0] +set_property IOSTANDARD LVCMOS33 [get_ports user_sw0] + ## user_sw:1 +set_property LOC C11 [get_ports user_sw1] +set_property IOSTANDARD LVCMOS33 [get_ports user_sw1] + ## user_sw:2 +set_property LOC C10 [get_ports user_sw2] +set_property IOSTANDARD LVCMOS33 [get_ports user_sw2] + ## user_sw:3 +set_property LOC A10 [get_ports user_sw3] +set_property IOSTANDARD LVCMOS33 [get_ports user_sw3] + ## user_btn:0 +set_property LOC D9 [get_ports user_btn0] +set_property IOSTANDARD LVCMOS33 [get_ports user_btn0] + ## user_btn:1 +set_property LOC C9 [get_ports user_btn1] +set_property IOSTANDARD LVCMOS33 [get_ports user_btn1] + ## user_btn:2 +set_property LOC B9 [get_ports user_btn2] +set_property IOSTANDARD LVCMOS33 [get_ports user_btn2] + ## user_btn:3 +set_property LOC B8 [get_ports user_btn3] +set_property IOSTANDARD LVCMOS33 [get_ports user_btn3] + ## spiflash_1x:0.cs_n +#set_property LOC L13 [get_ports spiflash_1x_cs_n] +#set_property IOSTANDARD LVCMOS33 [get_ports spiflash_1x_cs_n] +# ## spiflash_1x:0.mosi +#set_property LOC K17 [get_ports spiflash_1x_mosi] +#set_property IOSTANDARD LVCMOS33 [get_ports spiflash_1x_mosi] +# ## spiflash_1x:0.miso +#set_property LOC K18 [get_ports spiflash_1x_miso] +#set_property IOSTANDARD LVCMOS33 [get_ports spiflash_1x_miso] +# ## spiflash_1x:0.wp +#set_property LOC L14 [get_ports spiflash_1x_wp] +#set_property IOSTANDARD LVCMOS33 [get_ports spiflash_1x_wp] +# ## spiflash_1x:0.hold +#set_property LOC M14 [get_ports spiflash_1x_hold] +#set_property IOSTANDARD LVCMOS33 [get_ports spiflash_1x_hold] +# ## ddram:0.a +#set_property LOC R2 [get_ports ddram_a[0]] +#set_property SLEW FAST [get_ports ddram_a[0]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_a[0]] +# ## ddram:0.a +#set_property LOC M6 [get_ports ddram_a[1]] +#set_property SLEW FAST [get_ports ddram_a[1]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_a[1]] +# ## ddram:0.a +#set_property LOC N4 [get_ports ddram_a[2]] +#set_property SLEW FAST [get_ports ddram_a[2]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_a[2]] +# ## ddram:0.a +#set_property LOC T1 [get_ports ddram_a[3]] +#set_property SLEW FAST [get_ports ddram_a[3]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_a[3]] +# ## ddram:0.a +#set_property LOC N6 [get_ports ddram_a[4]] +#set_property SLEW FAST [get_ports ddram_a[4]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_a[4]] +# ## ddram:0.a +#set_property LOC R7 [get_ports ddram_a[5]] +#set_property SLEW FAST [get_ports ddram_a[5]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_a[5]] +# ## ddram:0.a +#set_property LOC V6 [get_ports ddram_a[6]] +#set_property SLEW FAST [get_ports ddram_a[6]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_a[6]] +# ## ddram:0.a +#set_property LOC U7 [get_ports ddram_a[7]] +#set_property SLEW FAST [get_ports ddram_a[7]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_a[7]] +# ## ddram:0.a +#set_property LOC R8 [get_ports ddram_a[8]] +#set_property SLEW FAST [get_ports ddram_a[8]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_a[8]] +# ## ddram:0.a +#set_property LOC V7 [get_ports ddram_a[9]] +#set_property SLEW FAST [get_ports ddram_a[9]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_a[9]] +# ## ddram:0.a +#set_property LOC R6 [get_ports ddram_a[10]] +#set_property SLEW FAST [get_ports ddram_a[10]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_a[10]] +# ## ddram:0.a +#set_property LOC U6 [get_ports ddram_a[11]] +#set_property SLEW FAST [get_ports ddram_a[11]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_a[11]] +# ## ddram:0.a +#set_property LOC T6 [get_ports ddram_a[12]] +#set_property SLEW FAST [get_ports ddram_a[12]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_a[12]] +# ## ddram:0.a +#set_property LOC T8 [get_ports ddram_a[13]] +#set_property SLEW FAST [get_ports ddram_a[13]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_a[13]] +# ## ddram:0.ba +#set_property LOC R1 [get_ports ddram_ba[0]] +#set_property SLEW FAST [get_ports ddram_ba[0]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_ba[0]] +# ## ddram:0.ba +#set_property LOC P4 [get_ports ddram_ba[1]] +#set_property SLEW FAST [get_ports ddram_ba[1]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_ba[1]] +# ## ddram:0.ba +#set_property LOC P2 [get_ports ddram_ba[2]] +#set_property SLEW FAST [get_ports ddram_ba[2]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_ba[2]] +# ## ddram:0.ras_n +#set_property LOC P3 [get_ports ddram_ras_n] +#set_property SLEW FAST [get_ports ddram_ras_n] +#set_property IOSTANDARD SSTL15 [get_ports ddram_ras_n] +# ## ddram:0.cas_n +#set_property LOC M4 [get_ports ddram_cas_n] +#set_property SLEW FAST [get_ports ddram_cas_n] +#set_property IOSTANDARD SSTL15 [get_ports ddram_cas_n] +# ## ddram:0.we_n +#set_property LOC P5 [get_ports ddram_we_n] +#set_property SLEW FAST [get_ports ddram_we_n] +#set_property IOSTANDARD SSTL15 [get_ports ddram_we_n] +# ## ddram:0.cs_n +#set_property LOC U8 [get_ports ddram_cs_n] +#set_property SLEW FAST [get_ports ddram_cs_n] +#set_property IOSTANDARD SSTL15 [get_ports ddram_cs_n] +# ## ddram:0.dm +#set_property LOC L1 [get_ports ddram_dm[0]] +#set_property SLEW FAST [get_ports ddram_dm[0]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_dm[0]] +# ## ddram:0.dm +#set_property LOC U1 [get_ports ddram_dm[1]] +#set_property SLEW FAST [get_ports ddram_dm[1]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_dm[1]] +# ## ddram:0.dq +#set_property LOC K5 [get_ports ddram_dq[0]] +#set_property SLEW FAST [get_ports ddram_dq[0]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[0]] +#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[0]] +# ## ddram:0.dq +#set_property LOC L3 [get_ports ddram_dq[1]] +#set_property SLEW FAST [get_ports ddram_dq[1]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[1]] +#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[1]] +# ## ddram:0.dq +#set_property LOC K3 [get_ports ddram_dq[2]] +#set_property SLEW FAST [get_ports ddram_dq[2]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[2]] +#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[2]] +# ## ddram:0.dq +#set_property LOC L6 [get_ports ddram_dq[3]] +#set_property SLEW FAST [get_ports ddram_dq[3]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[3]] +#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[3]] +# ## ddram:0.dq +#set_property LOC M3 [get_ports ddram_dq[4]] +#set_property SLEW FAST [get_ports ddram_dq[4]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[4]] +#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[4]] +# ## ddram:0.dq +#set_property LOC M1 [get_ports ddram_dq[5]] +#set_property SLEW FAST [get_ports ddram_dq[5]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[5]] +#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[5]] +# ## ddram:0.dq +#set_property LOC L4 [get_ports ddram_dq[6]] +#set_property SLEW FAST [get_ports ddram_dq[6]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[6]] +#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[6]] +# ## ddram:0.dq +#set_property LOC M2 [get_ports ddram_dq[7]] +#set_property SLEW FAST [get_ports ddram_dq[7]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[7]] +#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[7]] +# ## ddram:0.dq +#set_property LOC V4 [get_ports ddram_dq[8]] +#set_property SLEW FAST [get_ports ddram_dq[8]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[8]] +#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[8]] +# ## ddram:0.dq +#set_property LOC T5 [get_ports ddram_dq[9]] +#set_property SLEW FAST [get_ports ddram_dq[9]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[9]] +#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[9]] +# ## ddram:0.dq +#set_property LOC U4 [get_ports ddram_dq[10]] +#set_property SLEW FAST [get_ports ddram_dq[10]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[10]] +#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[10]] +# ## ddram:0.dq +#set_property LOC V5 [get_ports ddram_dq[11]] +#set_property SLEW FAST [get_ports ddram_dq[11]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[11]] +#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[11]] +# ## ddram:0.dq +#set_property LOC V1 [get_ports ddram_dq[12]] +#set_property SLEW FAST [get_ports ddram_dq[12]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[12]] +#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[12]] +# ## ddram:0.dq +#set_property LOC T3 [get_ports ddram_dq[13]] +#set_property SLEW FAST [get_ports ddram_dq[13]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[13]] +#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[13]] +# ## ddram:0.dq +#set_property LOC U3 [get_ports ddram_dq[14]] +#set_property SLEW FAST [get_ports ddram_dq[14]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[14]] +#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[14]] +# ## ddram:0.dq +#set_property LOC R3 [get_ports ddram_dq[15]] +#set_property SLEW FAST [get_ports ddram_dq[15]] +#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[15]] +#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[15]] +# ## ddram:0.dqs_p +#set_property LOC N2 [get_ports ddram_dqs_p[0]] +#set_property SLEW FAST [get_ports ddram_dqs_p[0]] +#set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_dqs_p[0]] +# ## ddram:0.dqs_p +#set_property LOC U2 [get_ports ddram_dqs_p[1]] +#set_property SLEW FAST [get_ports ddram_dqs_p[1]] +#set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_dqs_p[1]] +# ## ddram:0.dqs_n +#set_property LOC N1 [get_ports ddram_dqs_n[0]] +#set_property SLEW FAST [get_ports ddram_dqs_n[0]] +#set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_dqs_n[0]] +# ## ddram:0.dqs_n +#set_property LOC V2 [get_ports ddram_dqs_n[1]] +#set_property SLEW FAST [get_ports ddram_dqs_n[1]] +#set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_dqs_n[1]] +# ## ddram:0.clk_p +#set_property LOC U9 [get_ports ddram_clk_p] +#set_property SLEW FAST [get_ports ddram_clk_p] +#set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_clk_p] +# ## ddram:0.clk_n +#set_property LOC V9 [get_ports ddram_clk_n] +#set_property SLEW FAST [get_ports ddram_clk_n] +#set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_clk_n] +# ## ddram:0.cke +#set_property LOC N5 [get_ports ddram_cke] +#set_property SLEW FAST [get_ports ddram_cke] +#set_property IOSTANDARD SSTL15 [get_ports ddram_cke] +# ## ddram:0.odt +#set_property LOC R5 [get_ports ddram_odt] +#set_property SLEW FAST [get_ports ddram_odt] +#set_property IOSTANDARD SSTL15 [get_ports ddram_odt] +# ## ddram:0.reset_n +#set_property LOC K6 [get_ports ddram_reset_n] +#set_property SLEW FAST [get_ports ddram_reset_n] +#set_property IOSTANDARD SSTL15 [get_ports ddram_reset_n] +# ## eth_clocks:0.tx +#set_property LOC H16 [get_ports eth_clocks_tx] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_clocks_tx] +# ## eth_clocks:0.rx +#set_property LOC F15 [get_ports eth_clocks_rx] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_clocks_rx] +# ## eth:0.rst_n +#set_property LOC C16 [get_ports eth_rst_n] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_rst_n] +# ## eth:0.mdio +#set_property LOC K13 [get_ports eth_mdio] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_mdio] +# ## eth:0.mdc +#set_property LOC F16 [get_ports eth_mdc] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_mdc] +# ## eth:0.rx_dv +#set_property LOC G16 [get_ports eth_rx_dv] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_dv] +# ## eth:0.rx_er +#set_property LOC C17 [get_ports eth_rx_er] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_er] +# ## eth:0.rx_data +#set_property LOC D18 [get_ports eth_rx_data[0]] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_data[0]] +# ## eth:0.rx_data +#set_property LOC E17 [get_ports eth_rx_data[1]] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_data[1]] +# ## eth:0.rx_data +#set_property LOC E18 [get_ports eth_rx_data[2]] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_data[2]] +# ## eth:0.rx_data +#set_property LOC G17 [get_ports eth_rx_data[3]] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_data[3]] +# ## eth:0.tx_en +#set_property LOC H15 [get_ports eth_tx_en] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_en] +# ## eth:0.tx_data +#set_property LOC H14 [get_ports eth_tx_data[0]] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_data[0]] +# ## eth:0.tx_data +#set_property LOC J14 [get_ports eth_tx_data[1]] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_data[1]] +# ## eth:0.tx_data +#set_property LOC J13 [get_ports eth_tx_data[2]] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_data[2]] +# ## eth:0.tx_data +#set_property LOC H17 [get_ports eth_tx_data[3]] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_data[3]] +# ## eth:0.col +#set_property LOC D17 [get_ports eth_col] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_col] +# ## eth:0.crs +#set_property LOC G14 [get_ports eth_crs] +#set_property IOSTANDARD LVCMOS33 [get_ports eth_crs] + +set_property INTERNAL_VREF 0.750 [get_iobanks 34] + +create_clock -name sys_clk -period 10.0 [get_nets sys_clk] + +create_clock -name clk100 -period 10.0 [get_nets clk100] + +#create_clock -name eth_rx_clk -period 40.0 [get_nets eth_rx_clk] + +#create_clock -name eth_tx_clk -period 40.0 [get_nets eth_tx_clk] + +#set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_rx_clk]] -asynchronous + +#set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_tx_clk]] -asynchronous + +#set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets eth_rx_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_tx_clk]] -asynchronous + +set_false_path -quiet -to [get_nets -quiet -filter {mr_ff == TRUE}] + +set_false_path -quiet -to [get_pins -quiet -filter {REF_PIN_NAME == PRE} -of [get_cells -quiet -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]] + +set_max_delay 2 -quiet -from [get_pins -quiet -filter {REF_PIN_NAME == Q} -of [get_cells -quiet -filter {ars_ff1 == TRUE}]] -to [get_pins -quiet -filter {REF_PIN_NAME == D} -of [get_cells -quiet -filter {ars_ff2 == TRUE}]] diff --git a/VexRiscv/scripts/Murax/arty_a7/make_mcs_file b/VexRiscv/scripts/Murax/arty_a7/make_mcs_file new file mode 100755 index 0000000..40bcc5a --- /dev/null +++ b/VexRiscv/scripts/Murax/arty_a7/make_mcs_file @@ -0,0 +1,6 @@ +#!/bin/sh +#Create mcs file for QSPI flash + +cd ./build + +vivado -mode batch -source ../make_mcs_file.tcl -notrace diff --git a/VexRiscv/scripts/Murax/arty_a7/make_mmi_files b/VexRiscv/scripts/Murax/arty_a7/make_mmi_files new file mode 100755 index 0000000..3919e16 --- /dev/null +++ b/VexRiscv/scripts/Murax/arty_a7/make_mmi_files @@ -0,0 +1,4 @@ +#!/bin/sh + +cd ./build +vivado -mode batch -source ../make_mmi_files.tcl -notrace diff --git a/VexRiscv/scripts/Murax/arty_a7/make_vivado_project b/VexRiscv/scripts/Murax/arty_a7/make_vivado_project new file mode 100755 index 0000000..eb0f5a9 --- /dev/null +++ b/VexRiscv/scripts/Murax/arty_a7/make_vivado_project @@ -0,0 +1,9 @@ +#!/bin/sh + +#cannot rm build because it erase software images that the make file copy there +#rm -rf ./build + +mkdir -p ./build + +cd ./build +vivado -mode batch -source ../make_vivado_project.tcl -notrace diff --git a/VexRiscv/scripts/Murax/arty_a7/makefile b/VexRiscv/scripts/Murax/arty_a7/makefile new file mode 100644 index 0000000..b672652 --- /dev/null +++ b/VexRiscv/scripts/Murax/arty_a7/makefile @@ -0,0 +1,62 @@ +ROOT=../../.. +SWBASE=$(ROOT)/src/main/c/murax +SOCSW=hello_world +SOCMEMSRC=$(SWBASE)/$(SOCSW)/build/$(SOCSW).v +SOCMEM=build/soc.mem + +TOP=Murax + +all : build/latest.bit + +../../../$(TOP).v : toplevel.v + (cd ../../..; sbt "runMain vexriscv.demo.Murax_arty") + +.PHONY: $(SOCMEMSRC) +$(SOCMEMSRC): + mkdir -p build + make -C $(SWBASE)/$(SOCSW) + +$(SOCMEM) : $(SOCMEMSRC) + cp -u $(SOCMEMSRC) $(SOCMEM) + +build/vivado_project/fpga.runs/impl_1/toplevel.bit : toplevel.v arty_a7.xdc ../../../$(TOP).v + mkdir -p build + ./make_vivado_project + cp build/vivado_project/fpga.runs/impl_1/toplevel.bit build/latest.bit + +build/soc.mmi: build/vivado_project/fpga.runs/impl_1/toplevel.bit + ./make_mmi_files + +build/latest_soc_sw.bit : $(SOCMEM) build/soc.mmi + rm -f updatemem.jou updatemem.log + updatemem -force --meminfo build/soc.mmi --data $(SOCMEM) --bit build/latest.bit --proc dummy --out build/latest_soc_sw.bit + cp build/latest_soc_sw.bit build/latest.bit + +build/latest.bit : build/latest_soc_sw.bit + +build/latest.mcs : build/latest.bit + ./make_mcs_file + +prog : build/latest.bit + ./write_fpga + +flash : build/latest.mcs + ./write_flash + +clean-soc-sw: + make -C $(SWBASE)/$(SOCSW) clean-all + +soc-sw: clean-soc-sw $(SOCMEM) + +.PHONY: clean +clean : + rm -rf build + mkdir build + rm -f updatemem.jou + rm -f updatemem.log + +clean-sw: clean-soc-sw + +clean-all : clean clean-sw + rm -f ../../../$(TOP).v + rm -f ../../../$(TOP).v_* diff --git a/VexRiscv/scripts/Murax/arty_a7/open_vivado_project b/VexRiscv/scripts/Murax/arty_a7/open_vivado_project new file mode 100755 index 0000000..24c54d1 --- /dev/null +++ b/VexRiscv/scripts/Murax/arty_a7/open_vivado_project @@ -0,0 +1,4 @@ +#!/bin/sh + +cd ./build +vivado -mode batch -source ../open_vivado_project.tcl -notrace diff --git a/VexRiscv/scripts/Murax/arty_a7/picocom_arty b/VexRiscv/scripts/Murax/arty_a7/picocom_arty new file mode 100644 index 0000000..ff15a17 --- /dev/null +++ b/VexRiscv/scripts/Murax/arty_a7/picocom_arty @@ -0,0 +1 @@ +picocom --baud 115200 --imap lfcrlf /dev/ttyUSB1 diff --git a/VexRiscv/scripts/Murax/arty_a7/toplevel.v b/VexRiscv/scripts/Murax/arty_a7/toplevel.v new file mode 100644 index 0000000..e127da6 --- /dev/null +++ b/VexRiscv/scripts/Murax/arty_a7/toplevel.v @@ -0,0 +1,66 @@ +`timescale 1ns / 1ps + +module toplevel( + input wire clk100, + input wire cpu_reset,//active low + + input wire tck, + input wire tms, + input wire tdi, + input wire trst,//ignored + output reg tdo, + + input wire serial_rx, + output wire serial_tx, + + input wire user_sw0, + input wire user_sw1, + input wire user_sw2, + input wire user_sw3, + + input wire user_btn0, + input wire user_btn1, + input wire user_btn2, + input wire user_btn3, + + output wire user_led0, + output wire user_led1, + output wire user_led2, + output wire user_led3 + ); + + wire [31:0] io_gpioA_read; + wire [31:0] io_gpioA_write; + wire [31:0] io_gpioA_writeEnable; + + wire io_asyncReset = ~cpu_reset; + + assign {user_led3,user_led2,user_led1,user_led0} = io_gpioA_write[3 : 0]; + assign io_gpioA_read[3:0] = {user_sw3,user_sw2,user_sw1,user_sw0}; + assign io_gpioA_read[7:4] = {user_btn3,user_btn2,user_btn1,user_btn0}; + assign io_gpioA_read[11:8] = {tck,tms,tdi,trst}; + + reg tesic_tck,tesic_tms,tesic_tdi; + wire tesic_tdo; + reg soc_tck,soc_tms,soc_tdi; + wire soc_tdo; + + always @(*) begin + {soc_tck, soc_tms, soc_tdi } = {tck,tms,tdi}; + tdo = soc_tdo; + end + + Murax core ( + .io_asyncReset(io_asyncReset), + .io_mainClk (clk100 ), + .io_jtag_tck(soc_tck), + .io_jtag_tdi(soc_tdi), + .io_jtag_tdo(soc_tdo), + .io_jtag_tms(soc_tms), + .io_gpioA_read (io_gpioA_read), + .io_gpioA_write (io_gpioA_write), + .io_gpioA_writeEnable(io_gpioA_writeEnable), + .io_uart_txd(serial_tx), + .io_uart_rxd(serial_rx) + ); +endmodule diff --git a/VexRiscv/scripts/Murax/arty_a7/write_flash b/VexRiscv/scripts/Murax/arty_a7/write_flash new file mode 100755 index 0000000..05414c4 --- /dev/null +++ b/VexRiscv/scripts/Murax/arty_a7/write_flash @@ -0,0 +1,3 @@ +#!/bin/sh +cd ./build +vivado -mode batch -source ../write_flash.tcl -notrace diff --git a/VexRiscv/scripts/Murax/arty_a7/write_fpga b/VexRiscv/scripts/Murax/arty_a7/write_fpga new file mode 100755 index 0000000..63a344e --- /dev/null +++ b/VexRiscv/scripts/Murax/arty_a7/write_fpga @@ -0,0 +1,3 @@ +#!/bin/sh +cd ./build +vivado -mode batch -source ../write_fpga.tcl -notrace diff --git a/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board/Makefile b/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board/Makefile new file mode 100644 index 0000000..4689674 --- /dev/null +++ b/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board/Makefile @@ -0,0 +1,38 @@ + + +VERILOG = ../../../Murax.v toplevel.v + +generate : + (cd ../../..; sbt "runMain vexriscv.demo.MuraxWithRamInit") + +../../../Murax.v : + (cd ../../..; sbt "runMain vexriscv.demo.MuraxWithRamInit") + +../../../Murax.v*.bin: + +bin/toplevel.blif : ${VERILOG} ../../../Murax.v*.bin + mkdir -p bin + rm -f Murax.v*.bin + cp ../../../Murax.v*.bin . | true + yosys -v3 -p "synth_ice40 -top toplevel -blif bin/toplevel.blif" ${VERILOG} + +bin/toplevel.asc : toplevel.pcf bin/toplevel.blif + arachne-pnr -p toplevel.pcf -d 8k --max-passes 600 -P ct256 bin/toplevel.blif -o bin/toplevel.asc + +bin/toplevel.bin : bin/toplevel.asc + icepack bin/toplevel.asc bin/toplevel.bin + +compile : bin/toplevel.bin + +time: bin/toplevel.bin + icetime -tmd hx8k bin/toplevel.asc + +prog : bin/toplevel.bin + iceprog -S bin/toplevel.bin + +sudo-prog : bin/toplevel.bin + sudo iceprog -S bin/toplevel.bin + +clean : + rm -rf bin + rm -f Murax.v*.bin diff --git a/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board/README.md b/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board/README.md new file mode 100644 index 0000000..1e50a02 --- /dev/null +++ b/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board/README.md @@ -0,0 +1,86 @@ +This example is for the +[Lattice iCE40HX-8K Breakout Board](http://www.latticesemi.com/Products/DevelopmentBoardsAndKits/iCE40HX8KBreakoutBoard.aspx). + +An image of this board is shown below; + + + +This board can be purchased for ~$USD 49 directly from Lattice and is supported +by the IceStorm +[`iceprog`](https://github.com/cliffordwolf/icestorm/tree/master/iceprog) tool. + + +# Using the example + +## Before Starting + +Before starting make sure that your board is configured for `CRAM Programming` +mode. This requires removing jumper `J7` and putting the pair of jumpers on +`J6` to be parallel to the text on the board. + +This is shown in **Figure 5** of the +[iCE40HX-8K Breakout Board User Guide](http://www.latticesemi.com/view_document?document_id=50373). +which is also reproduced below; + + + +Once your board is ready, you should follow the setup instructions at the +[top level](../../../README.md). + +You should make sure you have the following tools installed; + * Yosys + * arachne-pnr + * icestorm tools (like icepack and iceprog) + * riscv toolchain + * sbt + +## Building + +You should be able to just type `make compile` and get output similar to this; +``` +... + place time 10.14s +route... + pass 1, 15 shared. + pass 2, 4 shared. + pass 3, 1 shared. + pass 4, 0 shared. + +After routing: +span_4 4406 / 29696 +span_12 951 / 5632 + + route time 9.12s +write_txt bin/toplevel.asc... +icepack bin/toplevel.asc bin/toplevel.bin +``` + +The process should take around 30 seconds on a reasonable fast computer. + +## Programming + +After building you should be able to run `make prog`. You may need to run `make +sudo-prog` if root is needed to access your USB devices. + +You should get output like the following; +``` +iceprog -S bin/toplevel.bin +init.. +cdone: high +reset.. +cdone: low +programming.. +cdone: high +Bye. +``` + +After programming the LEDs at the top of the board should start flashing in an +interesting pattern. + +## Connect + +After programming you should be able to connect to the serial port and have the +output echoed back to you. + +On Linux you can do this using a command like `screen /dev/ttyUSB1`. Then as +you type you should get back the same characters. diff --git a/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board/img/cram-programming-config.png b/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board/img/cram-programming-config.png Binary files differnew file mode 100644 index 0000000..48562bb --- /dev/null +++ b/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board/img/cram-programming-config.png diff --git a/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board/img/iCE40HX8K-breakout-revA.png b/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board/img/iCE40HX8K-breakout-revA.png Binary files differnew file mode 100644 index 0000000..2c460bb --- /dev/null +++ b/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board/img/iCE40HX8K-breakout-revA.png diff --git a/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board/toplevel.pcf b/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board/toplevel.pcf new file mode 100644 index 0000000..1f10124 --- /dev/null +++ b/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board/toplevel.pcf @@ -0,0 +1,19 @@ +## iCE40-hx8k breakout board + +set_io io_J3 J3 +set_io io_H16 H16 +set_io io_G15 G15 +set_io io_G16 G16 +set_io io_F15 F15 +set_io io_B12 B12 +set_io io_B10 B10 +set_io io_led[0] B5 +set_io io_led[1] B4 +set_io io_led[2] A2 +set_io io_led[3] A1 +set_io io_led[4] C5 +set_io io_led[5] C4 +set_io io_led[6] B3 +set_io io_led[7] C3 + + diff --git a/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board/toplevel.v b/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board/toplevel.v new file mode 100644 index 0000000..2643c30 --- /dev/null +++ b/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board/toplevel.v @@ -0,0 +1,45 @@ +`timescale 1ns / 1ps + +module toplevel( + input io_J3, + input io_H16, + input io_G15, + output io_G16, + input io_F15, + output io_B12, + input io_B10, + output [7:0] io_led + ); + + wire [31:0] io_gpioA_read; + wire [31:0] io_gpioA_write; + wire [31:0] io_gpioA_writeEnable; + wire io_mainClk; + wire io_jtag_tck; + + SB_GB mainClkBuffer ( + .USER_SIGNAL_TO_GLOBAL_BUFFER (io_J3), + .GLOBAL_BUFFER_OUTPUT ( io_mainClk) + ); + + SB_GB jtagClkBuffer ( + .USER_SIGNAL_TO_GLOBAL_BUFFER (io_H16), + .GLOBAL_BUFFER_OUTPUT ( io_jtag_tck) + ); + + assign io_led = io_gpioA_write[7 : 0]; + + Murax murax ( + .io_asyncReset(0), + .io_mainClk (io_mainClk ), + .io_jtag_tck(io_jtag_tck), + .io_jtag_tdi(io_G15), + .io_jtag_tdo(io_G16), + .io_jtag_tms(io_F15), + .io_gpioA_read (io_gpioA_read), + .io_gpioA_write (io_gpioA_write), + .io_gpioA_writeEnable(io_gpioA_writeEnable), + .io_uart_txd(io_B12), + .io_uart_rxd(io_B10) + ); +endmodule
\ No newline at end of file diff --git a/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board_xip/Makefile b/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board_xip/Makefile new file mode 100644 index 0000000..8feef20 --- /dev/null +++ b/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board_xip/Makefile @@ -0,0 +1,44 @@ + +VBASE = ../../.. +VNAME = Murax_iCE40_hx8k_breakout_board_xip +VERILOG = ${VBASE}/${VNAME}.v + +all: prog + +${VERILOG} : + (cd ${VBASE}; sbt "runMain vexriscv.demo.${VNAME}") + +generate : ${VERILOG} + +${VERILOG}*.bin: + +bin/Murax_iCE40_hx8k_breakout_board_xip.blif : ${VERILOG} ${VERILOG}*.bin + mkdir -p bin + rm -f Murax_iCE40_hx8k_breakout_board_xip.v*.bin + cp ${VERILOG}*.bin . | true + yosys -v3 -p "synth_ice40 -top Murax_iCE40_hx8k_breakout_board_xip -blif bin/Murax_iCE40_hx8k_breakout_board_xip.blif" ${VERILOG} + +bin/Murax_iCE40_hx8k_breakout_board_xip.asc : Murax_iCE40_hx8k_breakout_board_xip.pcf bin/Murax_iCE40_hx8k_breakout_board_xip.blif + arachne-pnr -p Murax_iCE40_hx8k_breakout_board_xip.pcf -d 8k --max-passes 600 -P ct256 bin/Murax_iCE40_hx8k_breakout_board_xip.blif -o bin/Murax_iCE40_hx8k_breakout_board_xip.asc + +bin/Murax_iCE40_hx8k_breakout_board_xip.bin : bin/Murax_iCE40_hx8k_breakout_board_xip.asc + icepack bin/Murax_iCE40_hx8k_breakout_board_xip.asc bin/Murax_iCE40_hx8k_breakout_board_xip.bin + +compile : bin/Murax_iCE40_hx8k_breakout_board_xip.bin + +time: bin/Murax_iCE40_hx8k_breakout_board_xip.bin + icetime -tmd hx8k bin/Murax_iCE40_hx8k_breakout_board_xip.asc + +prog : bin/Murax_iCE40_hx8k_breakout_board_xip.bin + lsusb -d 0403:6010 + iceprog -S bin/Murax_iCE40_hx8k_breakout_board_xip.bin + +sudo-prog : bin/Murax_iCE40_hx8k_breakout_board_xip.bin + sudo lsusb -d 0403:6010 + sudo iceprog -S bin/Murax_iCE40_hx8k_breakout_board_xip.bin + +clean : + rm -rf bin + rm -f Murax_iCE40_hx8k_breakout_board_xip.v*.bin + rm -f ${VERILOG}*.bin + rm -f ${VERILOG} diff --git a/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board_xip/Murax_iCE40_hx8k_breakout_board_xip.pcf b/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board_xip/Murax_iCE40_hx8k_breakout_board_xip.pcf new file mode 100644 index 0000000..510acf7 --- /dev/null +++ b/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board_xip/Murax_iCE40_hx8k_breakout_board_xip.pcf @@ -0,0 +1,23 @@ +## iCE40-hx8k breakout board + +set_io io_mainClk J3 +set_io io_jtag_tck H16 +set_io io_jtag_tdi G15 +set_io io_jtag_tdo G16 +set_io io_jtag_tms F15 +set_io io_uart_txd B12 +set_io io_uart_rxd B10 +set_io io_led[0] B5 +set_io io_led[1] B4 +set_io io_led[2] A2 +set_io io_led[3] A1 +set_io io_led[4] C5 +set_io io_led[5] C4 +set_io io_led[6] B3 +set_io io_led[7] C3 + +#XIP +set_io io_miso P12 +set_io io_mosi P11 +set_io io_sclk R11 +set_io io_spis R12 diff --git a/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board_xip/README.md b/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board_xip/README.md new file mode 100644 index 0000000..3ed77c5 --- /dev/null +++ b/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board_xip/README.md @@ -0,0 +1,207 @@ +This example is for the +[Lattice iCE40HX-8K Breakout Board](http://www.latticesemi.com/Products/DevelopmentBoardsAndKits/iCE40HX8KBreakoutBoard.aspx). + +An image of this board is shown below; + + + +This board can be purchased for ~$USD 49 directly from Lattice and is supported +by the IceStorm +[`iceprog`](https://github.com/cliffordwolf/icestorm/tree/master/iceprog) tool. + +# Bootloader operations + +A bootloader is implemented in a ROM within the FPGA bitfile. It configure the SPI and attempt to read the first word in 'XIP' area of the flash (0xE0040000 in CPU address space, 0x40000 in flash). If this first word is not 0xFFFFFFFF and the same value is read 3 times, +then the bootloader jump at 0xE0040000. + +# Using the example + +## Before Starting + +Before starting make sure that your board is configured for `CRAM Programming` +mode. This requires removing jumper `J7` and putting the pair of jumpers on +`J6` to be parallel to the text on the board. + +This is shown in **Figure 5** of the +[iCE40HX-8K Breakout Board User Guide](http://www.latticesemi.com/view_document?document_id=50373). +which is also reproduced below; + + + +Once your board is ready, you should follow the setup instructions at the +[top level](../../../README.md). + +You should make sure you have the following tools installed; + * Yosys + * arachne-pnr + * icestorm tools (like icepack and iceprog) + * riscv toolchain + * sbt + +## Building + +You should be able to just type `make compile` and get output similar to this; +``` +... + place time 10.14s +route... + pass 1, 15 shared. + pass 2, 4 shared. + pass 3, 1 shared. + pass 4, 0 shared. + +After routing: +span_4 4406 / 29696 +span_12 951 / 5632 + + route time 9.12s +write_txt bin/toplevel.asc... +icepack bin/toplevel.asc bin/toplevel.bin +``` + +The process should take around 30 seconds on a reasonable fast computer. + +## Programming + +Make sure the FPGA board is the only USB peripheral with ID 0403:6010 + +For example, this is bad: +``` +user@lafite:~$ lsusb -d 0403:6010 +Bus 001 Device 088: ID 0403:6010 Future Technology Devices International, Ltd FT2232C Dual USB-UART/FIFO IC +Bus 001 Device 090: ID 0403:6010 Future Technology Devices International, Ltd FT2232C Dual USB-UART/FIFO IC +``` +This is good: +``` +user@lafite:~$ lsusb -d 0403:6010 +Bus 001 Device 088: ID 0403:6010 Future Technology Devices International, Ltd FT2232C Dual USB-UART/FIFO IC +``` + + +After building you should be able to run `make prog`. You may need to run `make +sudo-prog` if root is needed to access your USB devices. + +You should get output like the following; +``` +lsusb -d 0403:6010 +Bus 001 Device 088: ID 0403:6010 Future Technology Devices International, Ltd FT2232C Dual USB-UART/FIFO IC +iceprog -S bin/Murax_iCE40_hx8k_breakout_board_xip.bin +init.. +cdone: high +reset.. +cdone: low +programming.. +cdone: high +Bye. +``` + +WARNING: having this output does NOT guarantee you actually programmed anything in the FPGA! + +After programming nothing visual will happen, except the LEDs being off. +The bootloader is waiting for a valid content in the flash (see Bootloader operations). + +## Programming flash image + +### Connect JTAG + +We will use vexrisc JTAG to program the flash, so you need openocd and a +suitable JTAG dongle. + +Pin-out: +``` +TCK: H16 aka J2.25 +TDO: G16 aka J2.26 +TDI: G15 aka J2.27 +TMS: F15 aka J2.28 +``` +In addition you need to connect the ground and VTarget aka VIO: J2.2 on the +board. + +### Start GDB server / OpenOCD +Make sure to use https://github.com/SpinalHDL/openocd_riscv +Make sure to select the configuration file which match your JTAG dongle. + +An example with the dongle "ft2232h_breakout": +``` +src/openocd -f tcl/interface/ftdi/ft2232h_breakout.cfg -c "set MURAX_CPU0_YAML ../VexRiscv/cpu0.yaml" -f tcl/target/murax_xip.cfg +``` + +You should get an output like below: +``` +Open On-Chip Debugger 0.10.0+dev-01214-g0ace94f (2019-10-02-18:23) +Licensed under GNU GPL v2 +For bug reports, read + http://openocd.org/doc/doxygen/bugs.html +../VexRiscv/cpu0.yaml +adapter speed: 100 kHz +adapter_nsrst_delay: 260 +Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'. +jtag_ntrst_delay: 250 +Info : set servers polling period to 50ms +Error: libusb_get_string_descriptor_ascii() failed with LIBUSB_ERROR_INVALID_PARAM +Info : clock speed 100 kHz +Info : JTAG tap: fpga_spinal.bridge tap/device found: 0x10001fff (mfg: 0x7ff (<invalid>), part: 0x0001, ver: 0x1) +Info : Listening on port 3333 for gdb connections +requesting target halt and executing a soft reset +Info : Listening on port 6666 for tcl connections +Info : Listening on port 4444 for telnet connections +``` + +### Loading the flash with telnet + +First we connect and stop execution on the device: +``` +user@lafite:~/Downloads/vexrisc_full/VexRiscv/src/main/c/murax/xipBootloader$ telnet 127.0.0.1 4444 +Trying 127.0.0.1... +Connected to 127.0.0.1. +Escape character is '^]'. +Open On-Chip Debugger +> reset +JTAG tap: fpga_spinal.bridge tap/device found: 0x10001fff (mfg: 0x7ff (<invalid>), part: 0x0001, ver: 0x1) +> +``` + +Now we can safely connect the J7 jumper on the board to be able to access the flash. +After that, we can load the program in flash: +``` +> flash erase_sector 0 4 4 +erased sectors 4 through 4 on flash bank 0 in 0.872235s +> flash write_bank 0 /home/user/dev/vexrisc_fork/VexRiscv/src/main/c/murax/xipBootloader/demo_xip.bin 0x40000 +wrote 48 bytes from file /home/user/dev/vexrisc_fork/VexRiscv/src/main/c/murax/xipBootloader/demo_xip.bin to flash bank 0 at offset 0x00040000 in 0.285539s (0.164 KiB/s) +> flash verify_bank 0 /home/user/dev/vexrisc_fork/VexRiscv/src/main/c/murax/xipBootloader/demo_xip.bin 0x40000 +read 48 bytes from file /home/user/dev/vexrisc_fork/VexRiscv/src/main/c/murax/xipBootloader/demo_xip.bin and flash bank 0 at offset 0x00040000 in 0.192036s (0.244 KiB/s) +contents match +> reset +JTAG tap: fpga_spinal.bridge tap/device found: 0x10001fff (mfg: 0x7ff (<invalid>), part: 0x0001, ver: 0x1) +> resume +> exit +Connection closed by foreign host. +``` + +From now the device runs the code from flash, LEDs shall display a dot moving from D9 to D2. + +### Loading flash using GDB / eclipse +``` +src/openocd -f tcl/interface/ftdi/ft2232h_breakout.cfg -c "set MURAX_CPU0_YAML ../VexRiscv/cpu0.yaml" -f tcl/target/murax_xip.cfg +``` +- Make sure J7 is connected. +- Connect to GDB / eclipse as usual. + +From there code loading, step, break points works as usual (including software break points in flash). + +## Update hardware/bootloader + +- Stop any OpenOCD connection +- Remove J7, then: +``` +make clean prog +``` +- Remember to check a single FTDI device is listed in the output. If not: + - Disconnect the other devices + ``` + make prog + ``` +- Connect J7, flash software shall start executing. + +## Flash software +Refer to "Loading the flash with telnet" or "Loading flash using GDB / eclipse". diff --git a/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board_xip/img/cram-programming-config.png b/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board_xip/img/cram-programming-config.png Binary files differnew file mode 100644 index 0000000..48562bb --- /dev/null +++ b/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board_xip/img/cram-programming-config.png diff --git a/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board_xip/img/iCE40HX8K-breakout-revA.png b/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board_xip/img/iCE40HX8K-breakout-revA.png Binary files differnew file mode 100644 index 0000000..2c460bb --- /dev/null +++ b/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board_xip/img/iCE40HX8K-breakout-revA.png diff --git a/VexRiscv/scripts/Murax/iCE40HX8K-EVB/Makefile b/VexRiscv/scripts/Murax/iCE40HX8K-EVB/Makefile new file mode 100644 index 0000000..e90ed02 --- /dev/null +++ b/VexRiscv/scripts/Murax/iCE40HX8K-EVB/Makefile @@ -0,0 +1,38 @@ + + +VERILOG = ../../../Murax.v toplevel.v toplevel_pll.v + +generate : + (cd ../../..; sbt "runMain vexriscv.demo.MuraxWithRamInit") + +../../../Murax.v : + (cd ../../..; sbt "runMain vexriscv.demo.MuraxWithRamInit") + +../../../Murax.v*.bin: + +bin/toplevel.blif : ${VERILOG} ../../../Murax.v*.bin + mkdir -p bin + rm -f Murax.v*.bin + cp ../../../Murax.v*.bin . | true + yosys -v3 -p "synth_ice40 -top toplevel -blif bin/toplevel.blif" ${VERILOG} + +bin/toplevel.asc : toplevel.pcf bin/toplevel.blif + arachne-pnr -p toplevel.pcf -d 8k --max-passes 600 -P ct256 bin/toplevel.blif -o bin/toplevel.asc + +bin/toplevel.bin : bin/toplevel.asc + icepack bin/toplevel.asc bin/toplevel.bin + +compile : bin/toplevel.bin + +time: bin/toplevel.bin + icetime -tmd hx8k bin/toplevel.asc + +prog : bin/toplevel.bin + iceprogduino bin/toplevel.bin + +sudo-prog : bin/toplevel.bin + sudo iceprogduino bin/toplevel.bin + +clean : + rm -rf bin + rm -f Murax.v*.bin diff --git a/VexRiscv/scripts/Murax/iCE40HX8K-EVB/toplevel.pcf b/VexRiscv/scripts/Murax/iCE40HX8K-EVB/toplevel.pcf new file mode 100644 index 0000000..1a627d9 --- /dev/null +++ b/VexRiscv/scripts/Murax/iCE40HX8K-EVB/toplevel.pcf @@ -0,0 +1,5 @@ +set_io CLK J3 +set_io BUT1 K11 +set_io BUT2 P13 +set_io LED1 M12 +set_io LED2 R16 diff --git a/VexRiscv/scripts/Murax/iCE40HX8K-EVB/toplevel.v b/VexRiscv/scripts/Murax/iCE40HX8K-EVB/toplevel.v new file mode 100644 index 0000000..7058c11 --- /dev/null +++ b/VexRiscv/scripts/Murax/iCE40HX8K-EVB/toplevel.v @@ -0,0 +1,39 @@ +`timescale 1ns / 1ps + +module toplevel( + input CLK, + input BUT1, + input BUT2, + output LED1, + output LED2 + ); + + assign LED1 = io_gpioA_write[0]; + assign LED2 = io_gpioA_write[7]; + + wire [31:0] io_gpioA_read; + wire [31:0] io_gpioA_write; + wire [31:0] io_gpioA_writeEnable; + wire io_mainClk; + + // Use PLL to downclock external clock. + toplevel_pll toplevel_pll_inst(.REFERENCECLK(CLK), + .PLLOUTCORE(io_mainClk), + .PLLOUTGLOBAL(), + .RESET(1'b1)); + + Murax murax ( + .io_asyncReset(1'b0), + .io_mainClk (io_mainClk), + .io_jtag_tck(1'b0), + .io_jtag_tdi(1'b0), + .io_jtag_tdo(), + .io_jtag_tms(1'b0), + .io_gpioA_read (io_gpioA_read), + .io_gpioA_write (io_gpioA_write), + .io_gpioA_writeEnable(io_gpioA_writeEnable), + .io_uart_txd(), + .io_uart_rxd(0'b0) + ); + +endmodule diff --git a/VexRiscv/scripts/Murax/iCE40HX8K-EVB/toplevel_pll.v b/VexRiscv/scripts/Murax/iCE40HX8K-EVB/toplevel_pll.v new file mode 100644 index 0000000..e6df6b2 --- /dev/null +++ b/VexRiscv/scripts/Murax/iCE40HX8K-EVB/toplevel_pll.v @@ -0,0 +1,38 @@ +module toplevel_pll(REFERENCECLK, + PLLOUTCORE, + PLLOUTGLOBAL, + RESET); + +input REFERENCECLK; +input RESET; /* To initialize the simulation properly, the RESET signal (Active Low) must be asserted at the beginning of the simulation */ +output PLLOUTCORE; +output PLLOUTGLOBAL; + +SB_PLL40_CORE toplevel_pll_inst(.REFERENCECLK(REFERENCECLK), + .PLLOUTCORE(PLLOUTCORE), + .PLLOUTGLOBAL(PLLOUTGLOBAL), + .EXTFEEDBACK(), + .DYNAMICDELAY(), + .RESETB(RESET), + .BYPASS(1'b0), + .LATCHINPUTVALUE(), + .LOCK(), + .SDI(), + .SDO(), + .SCLK()); + +//\\ Fin=100, Fout=12; +defparam toplevel_pll_inst.DIVR = 4'b0010; +defparam toplevel_pll_inst.DIVF = 7'b0010110; +defparam toplevel_pll_inst.DIVQ = 3'b110; +defparam toplevel_pll_inst.FILTER_RANGE = 3'b011; +defparam toplevel_pll_inst.FEEDBACK_PATH = "SIMPLE"; +defparam toplevel_pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED"; +defparam toplevel_pll_inst.FDA_FEEDBACK = 4'b0000; +defparam toplevel_pll_inst.DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED"; +defparam toplevel_pll_inst.FDA_RELATIVE = 4'b0000; +defparam toplevel_pll_inst.SHIFTREG_DIV_MODE = 2'b00; +defparam toplevel_pll_inst.PLLOUT_SELECT = "GENCLK"; +defparam toplevel_pll_inst.ENABLE_ICEGATE = 1'b0; + +endmodule |
