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-rw-r--r--VexRiscv/src/test/cpp/raw/lrsc/.gitignore4
-rw-r--r--VexRiscv/src/test/cpp/raw/lrsc/build/lrsc.asm180
-rw-r--r--VexRiscv/src/test/cpp/raw/lrsc/build/lrsc.hex40
-rw-r--r--VexRiscv/src/test/cpp/raw/lrsc/makefile5
-rw-r--r--VexRiscv/src/test/cpp/raw/lrsc/src/crt.S213
-rw-r--r--VexRiscv/src/test/cpp/raw/lrsc/src/ld16
6 files changed, 458 insertions, 0 deletions
diff --git a/VexRiscv/src/test/cpp/raw/lrsc/.gitignore b/VexRiscv/src/test/cpp/raw/lrsc/.gitignore
new file mode 100644
index 0000000..c12cb2c
--- /dev/null
+++ b/VexRiscv/src/test/cpp/raw/lrsc/.gitignore
@@ -0,0 +1,4 @@
+*.map
+*.v
+*.elf
+*.o \ No newline at end of file
diff --git a/VexRiscv/src/test/cpp/raw/lrsc/build/lrsc.asm b/VexRiscv/src/test/cpp/raw/lrsc/build/lrsc.asm
new file mode 100644
index 0000000..a2ba4c7
--- /dev/null
+++ b/VexRiscv/src/test/cpp/raw/lrsc/build/lrsc.asm
@@ -0,0 +1,180 @@
+
+build/lrsc.elf: file format elf32-littleriscv
+
+
+Disassembly of section .crt_section:
+
+80000000 <trap_entry-0x20>:
+80000000: 06c0006f j 8000006c <_start>
+80000004: 00000013 nop
+80000008: 00000013 nop
+8000000c: 00000013 nop
+80000010: 00000013 nop
+80000014: 00000013 nop
+80000018: 00000013 nop
+8000001c: 00000013 nop
+
+80000020 <trap_entry>:
+80000020: 30002ef3 csrr t4,mstatus
+80000024: 080efe93 andi t4,t4,128
+80000028: 000e8a63 beqz t4,8000003c <notExternalInterrupt>
+8000002c: 00002eb7 lui t4,0x2
+80000030: 800e8e93 addi t4,t4,-2048 # 1800 <trap_entry-0x7fffe820>
+80000034: 300e9073 csrw mstatus,t4
+80000038: 30200073 mret
+
+8000003c <notExternalInterrupt>:
+8000003c: 34102ef3 csrr t4,mepc
+80000040: 004e8e93 addi t4,t4,4
+80000044: 341e9073 csrw mepc,t4
+80000048: 30200073 mret
+
+8000004c <flush>:
+8000004c: 200002b7 lui t0,0x20000
+80000050: 00001337 lui t1,0x1
+80000054: 02000393 li t2,32
+
+80000058 <flushLoop>:
+80000058: 0002ae03 lw t3,0(t0) # 20000000 <trap_entry-0x60000020>
+8000005c: 006282b3 add t0,t0,t1
+80000060: fff38393 addi t2,t2,-1
+80000064: fe039ae3 bnez t2,80000058 <flushLoop>
+80000068: 00008067 ret
+
+8000006c <_start>:
+8000006c: 00100e13 li t3,1
+80000070: 10000537 lui a0,0x10000
+80000074: 06400593 li a1,100
+80000078: 06500613 li a2,101
+8000007c: 06600693 li a3,102
+80000080: 00d52023 sw a3,0(a0) # 10000000 <trap_entry-0x70000020>
+80000084: 18b5262f sc.w a2,a1,(a0)
+80000088: 00100713 li a4,1
+8000008c: 18e61863 bne a2,a4,8000021c <fail>
+80000090: 00052703 lw a4,0(a0)
+80000094: 18e69463 bne a3,a4,8000021c <fail>
+
+80000098 <test2>:
+80000098: 00200e13 li t3,2
+8000009c: 10000537 lui a0,0x10000
+800000a0: 00450513 addi a0,a0,4 # 10000004 <trap_entry-0x7000001c>
+800000a4: 06700593 li a1,103
+800000a8: 06800613 li a2,104
+800000ac: 06900693 li a3,105
+800000b0: 00d52023 sw a3,0(a0)
+800000b4: 18b5262f sc.w a2,a1,(a0)
+800000b8: 00100713 li a4,1
+800000bc: 16e61063 bne a2,a4,8000021c <fail>
+800000c0: 00052703 lw a4,0(a0)
+800000c4: 14e69c63 bne a3,a4,8000021c <fail>
+800000c8: f85ff0ef jal ra,8000004c <flush>
+800000cc: 00052703 lw a4,0(a0)
+800000d0: 14e69663 bne a3,a4,8000021c <fail>
+
+800000d4 <test3>:
+800000d4: 00300e13 li t3,3
+800000d8: 10000537 lui a0,0x10000
+800000dc: 00450513 addi a0,a0,4 # 10000004 <trap_entry-0x7000001c>
+800000e0: 06700593 li a1,103
+800000e4: 06800613 li a2,104
+800000e8: 06900693 li a3,105
+800000ec: 18b5262f sc.w a2,a1,(a0)
+800000f0: 00100713 li a4,1
+800000f4: 12e61463 bne a2,a4,8000021c <fail>
+800000f8: 00052703 lw a4,0(a0)
+800000fc: 12e69063 bne a3,a4,8000021c <fail>
+80000100: f4dff0ef jal ra,8000004c <flush>
+80000104: 00052703 lw a4,0(a0)
+80000108: 10e69a63 bne a3,a4,8000021c <fail>
+
+8000010c <test4>:
+8000010c: 00400e13 li t3,4
+80000110: 10000537 lui a0,0x10000
+80000114: 00850513 addi a0,a0,8 # 10000008 <trap_entry-0x70000018>
+80000118: 06a00593 li a1,106
+8000011c: 06b00613 li a2,107
+80000120: 06c00693 li a3,108
+80000124: 00d52023 sw a3,0(a0)
+80000128: 100527af lr.w a5,(a0)
+8000012c: 18b5262f sc.w a2,a1,(a0)
+80000130: 0ed79663 bne a5,a3,8000021c <fail>
+80000134: 0e061463 bnez a2,8000021c <fail>
+80000138: 00052703 lw a4,0(a0)
+8000013c: 0ee59063 bne a1,a4,8000021c <fail>
+80000140: f0dff0ef jal ra,8000004c <flush>
+80000144: 00052703 lw a4,0(a0)
+80000148: 0ce59a63 bne a1,a4,8000021c <fail>
+
+8000014c <test5>:
+8000014c: 00500e13 li t3,5
+80000150: 10000537 lui a0,0x10000
+80000154: 00850513 addi a0,a0,8 # 10000008 <trap_entry-0x70000018>
+80000158: 06d00593 li a1,109
+8000015c: 06e00613 li a2,110
+80000160: 06f00693 li a3,111
+80000164: 00d52023 sw a3,0(a0)
+80000168: 18b5262f sc.w a2,a1,(a0)
+8000016c: 0a060863 beqz a2,8000021c <fail>
+80000170: 00052703 lw a4,0(a0)
+80000174: 0ae69463 bne a3,a4,8000021c <fail>
+80000178: ed5ff0ef jal ra,8000004c <flush>
+8000017c: 00052703 lw a4,0(a0)
+80000180: 08e69e63 bne a3,a4,8000021c <fail>
+80000184: 00700e13 li t3,7
+80000188: 10000537 lui a0,0x10000
+8000018c: 01450513 addi a0,a0,20 # 10000014 <trap_entry-0x7000000c>
+80000190: 07800593 li a1,120
+80000194: 07900613 li a2,121
+80000198: 07a00693 li a3,122
+8000019c: 01000e93 li t4,16
+
+800001a0 <test7>:
+800001a0: 00d52023 sw a3,0(a0)
+800001a4: 100527af lr.w a5,(a0)
+800001a8: 18b5262f sc.w a2,a1,(a0)
+800001ac: 06d79863 bne a5,a3,8000021c <fail>
+800001b0: 06061663 bnez a2,8000021c <fail>
+800001b4: 00052703 lw a4,0(a0)
+800001b8: 06e59263 bne a1,a4,8000021c <fail>
+800001bc: fffe8e93 addi t4,t4,-1
+800001c0: 00450513 addi a0,a0,4
+800001c4: 00358593 addi a1,a1,3
+800001c8: 00360613 addi a2,a2,3
+800001cc: 00368693 addi a3,a3,3
+800001d0: fc0e98e3 bnez t4,800001a0 <test7>
+
+800001d4 <test9>:
+800001d4: 00900e13 li t3,9
+800001d8: 10000537 lui a0,0x10000
+800001dc: 10050513 addi a0,a0,256 # 10000100 <trap_entry-0x6fffff20>
+800001e0: 07b00593 li a1,123
+800001e4: 07c00613 li a2,124
+800001e8: 07d00693 li a3,125
+800001ec: 00d52023 sw a3,0(a0)
+800001f0: 100527af lr.w a5,(a0)
+800001f4: 00000073 ecall
+800001f8: 18b527af sc.w a5,a1,(a0)
+800001fc: 00000713 li a4,0
+80000200: 00e79e63 bne a5,a4,8000021c <fail>
+80000204: 00052703 lw a4,0(a0)
+80000208: 00e59a63 bne a1,a4,8000021c <fail>
+8000020c: e41ff0ef jal ra,8000004c <flush>
+80000210: 00052703 lw a4,0(a0)
+80000214: 00e59463 bne a1,a4,8000021c <fail>
+80000218: 0100006f j 80000228 <pass>
+
+8000021c <fail>:
+8000021c: f0100137 lui sp,0xf0100
+80000220: f2410113 addi sp,sp,-220 # f00fff24 <pass+0x700ffcfc>
+80000224: 01c12023 sw t3,0(sp)
+
+80000228 <pass>:
+80000228: f0100137 lui sp,0xf0100
+8000022c: f2010113 addi sp,sp,-224 # f00fff20 <pass+0x700ffcf8>
+80000230: 00012023 sw zero,0(sp)
+80000234: 00000013 nop
+80000238: 00000013 nop
+8000023c: 00000013 nop
+80000240: 00000013 nop
+80000244: 00000013 nop
+80000248: 00000013 nop
diff --git a/VexRiscv/src/test/cpp/raw/lrsc/build/lrsc.hex b/VexRiscv/src/test/cpp/raw/lrsc/build/lrsc.hex
new file mode 100644
index 0000000..b0ee273
--- /dev/null
+++ b/VexRiscv/src/test/cpp/raw/lrsc/build/lrsc.hex
@@ -0,0 +1,40 @@
+:0200000480007A
+:100000006F00C00613000000130000001300000082
+:100010001300000013000000130000001300000094
+:10002000F32E003093FE0E08638A0E00B72E0000F8
+:10003000938E0E8073900E3073002030F32E1034A8
+:10004000938E4E0073901E3473002030B702002050
+:10005000371300009303000203AE0200B382620074
+:100060009383F3FFE39A03FE67800000130E1000F2
+:1000700037050010930540061306500693066006E8
+:100080002320D5002F26B518130710006318E61893
+:10009000032705006394E618130E200037050010AF
+:1000A0001305450093057006130680069306900617
+:1000B0002320D5002F26B518130710006310E6166D
+:1000C00003270500639CE614EFF05FF803270500A3
+:1000D0006396E614130E3000370500101305450033
+:1000E0009305700613068006930690062F26B51812
+:1000F000130710006314E612032705006390E6124D
+:10010000EFF0DFF403270500639AE610130E4000BA
+:1001100037050010130585009305A0061306B006E9
+:100120009306C0062320D500AF2705102F26B5184B
+:100130006396D70E6314060E032705006390E50E41
+:10014000EFF0DFF003270500639AE50C130E500073
+:1001500037050010130585009305D0061306E00649
+:100160009306F0062320D5002F26B5186308060A4B
+:10017000032705006394E60AEFF05FED032705000F
+:10018000639EE608130E7000370500101305450145
+:1001900093058007130690079306A007930E0001AE
+:1001A0002320D500AF2705102F26B5186398D70652
+:1001B00063160606032705006392E506938EFEFF8D
+:1001C00013054500938535001306360093863600E7
+:1001D000E3980EFC130E9000370500101305051070
+:1001E0009305B0071306C0079306D0072320D50058
+:1001F000AF27051073000000AF27B51813070000E4
+:10020000639EE70003270500639AE500EFF01FE413
+:10021000032705006394E5006F000001370110F02B
+:10022000130141F22320C101370110F0130101F243
+:100230002320010013000000130000001300000041
+:0C02400013000000130000001300000079
+:040000058000006C0B
+:00000001FF
diff --git a/VexRiscv/src/test/cpp/raw/lrsc/makefile b/VexRiscv/src/test/cpp/raw/lrsc/makefile
new file mode 100644
index 0000000..eafdb26
--- /dev/null
+++ b/VexRiscv/src/test/cpp/raw/lrsc/makefile
@@ -0,0 +1,5 @@
+PROJ_NAME=lrsc
+
+ATOMIC=yes
+
+include ../common/asm.mk \ No newline at end of file
diff --git a/VexRiscv/src/test/cpp/raw/lrsc/src/crt.S b/VexRiscv/src/test/cpp/raw/lrsc/src/crt.S
new file mode 100644
index 0000000..a19663f
--- /dev/null
+++ b/VexRiscv/src/test/cpp/raw/lrsc/src/crt.S
@@ -0,0 +1,213 @@
+.globl _start
+
+
+ j _start
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+
+.global trap_entry
+trap_entry:
+ csrr x29, mstatus
+ and x29, x29, 0x080
+ beqz x29, notExternalInterrupt
+ li x29, 0x1800 //000 disable interrupts
+ csrw mstatus,x29
+ mret
+
+notExternalInterrupt:
+ csrr x29, mepc
+ addi x29, x29, 4
+ csrw mepc, x29
+ mret
+
+flush:
+ li t0, 0x20000000
+ li t1, 0x1000
+ li t2, 32
+flushLoop:
+ lw t3, 0(t0)
+ add t0, t0, t1
+ addi t2,t2,-1
+ bnez t2, flushLoop
+ ret
+
+_start:
+test1: //Test 1 SC on unreserved area should fail and not write memory
+ li x28, 1
+ li a0, 0x10000000
+ li a1, 100
+ li a2, 101
+ li a3, 102
+ sw a3, 0(a0)
+ sc.w a2, a1, (a0)
+ li a4, 1
+ bne a2, a4, fail
+ lw a4, 0(a0)
+ bne a3, a4, fail
+
+test2: //Test 2 SC on another unreserved area should fail and not write memory
+ li x28, 2
+ li a0, 0x10000004
+ li a1, 103
+ li a2, 104
+ li a3, 105
+ sw a3, 0(a0)
+ sc.w a2, a1, (a0)
+ li a4, 1
+ bne a2, a4, fail
+ lw a4, 0(a0)
+ bne a3, a4, fail
+ call flush
+ lw a4, 0(a0)
+ bne a3, a4, fail
+
+
+test3: //Test 3 retrying SC on unreserved area should fail and not write memory
+ li x28, 3
+ li a0, 0x10000004
+ li a1, 103
+ li a2, 104
+ li a3, 105
+ sc.w a2, a1, (a0)
+ li a4, 1
+ bne a2, a4, fail
+ lw a4, 0(a0)
+ bne a3, a4, fail
+ call flush
+ lw a4, 0(a0)
+ bne a3, a4, fail
+
+
+test4: //Test 4 SC on reserved area should pass and should be written write memory
+ li x28, 4
+ li a0, 0x10000008
+ li a1, 106
+ li a2, 107
+ li a3, 108
+ sw a3, 0(a0)
+ lr.w a5, (a0)
+ sc.w a2, a1, (a0)
+ bne a5, a3, fail
+ bne a2, x0, fail
+ lw a4, 0(a0)
+ bne a1, a4, fail
+ call flush
+ lw a4, 0(a0)
+ bne a1, a4, fail
+
+
+test5: //Test 5 redo SC on reserved area should fail
+ li x28, 5
+ li a0, 0x10000008
+ li a1, 109
+ li a2, 110
+ li a3, 111
+ sw a3, 0(a0)
+ sc.w a2, a1, (a0)
+ beq a2, x0, fail
+ lw a4, 0(a0)
+ bne a3, a4, fail
+ call flush
+ lw a4, 0(a0)
+ bne a3, a4, fail
+
+
+//Test 7 do a lot of allocation to clear the entries
+ li x28, 7
+ li a0, 0x10000014
+ li a1, 120
+ li a2, 121
+ li a3, 122
+ li x29, 16
+test7:
+ sw a3, 0(a0)
+ lr.w a5, (a0)
+ sc.w a2, a1, (a0)
+ bne a5, a3, fail
+ bne a2, x0, fail
+ lw a4, 0(a0)
+ bne a1, a4, fail
+ add x29, x29, -1
+ add a0, a0, 4
+ add a1, a1, 3
+ add a2, a2, 3
+ add a3, a3, 3
+ bnez x29, test7
+
+
+//Test 8 SC on discarded entries should fail
+ /* li x28, 8
+ li a0, 0x10000018
+ li a1, 120
+ li a2, 121
+ li a3, 122
+ lw a5, 0(a0)
+ sc.w a2, a1, (a0)
+ li a4, 1
+ bne a2, a4, fail
+ lw a4, 0(a0)
+ bne a5, a4, fail*/
+
+
+test9: //Test 9 SC should pass after a context switching
+ li x28, 9
+ li a0, 0x10000100
+ li a1, 123
+ li a2, 124
+ li a3, 125
+ sw a3, 0(a0)
+ lr.w a5, (a0)
+ scall
+ sc.w a5, a1, (a0)
+ li a4, 0
+ bne a5, a4, fail
+ lw a4, 0(a0)
+ bne a1, a4, fail
+ call flush
+ lw a4, 0(a0)
+ bne a1, a4, fail
+
+
+
+//Test 10 SC should fail if the address doesn't match
+ /* li x28, 10
+ li a0, 0x10000200
+ li a6, 0x10000204
+ li a1, 126
+ li a2, 127
+ li a3, 128
+ li a7, 129
+ sw a3, 0(a0)
+ sw a7, 0(a6)
+ lr.w a5, (a6)
+ sc.w a2, a1, (a0)
+ li a4, 1
+ bne a2, a4, fail
+ lw a4, 0(a6)
+ bne a7, a4, fail*/
+
+
+ j pass
+
+
+fail: //x28 => error code
+ li x2, 0xF00FFF24
+ sw x28, 0(x2)
+
+pass:
+ li x2, 0xF00FFF20
+ sw x0, 0(x2)
+
+
+
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
diff --git a/VexRiscv/src/test/cpp/raw/lrsc/src/ld b/VexRiscv/src/test/cpp/raw/lrsc/src/ld
new file mode 100644
index 0000000..93d8de8
--- /dev/null
+++ b/VexRiscv/src/test/cpp/raw/lrsc/src/ld
@@ -0,0 +1,16 @@
+OUTPUT_ARCH( "riscv" )
+
+MEMORY {
+ onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 128K
+}
+
+SECTIONS
+{
+
+ .crt_section :
+ {
+ . = ALIGN(4);
+ *crt.o(.text)
+ } > onChipRam
+
+}
generated by cgit v1.2.3 (git 2.25.1) at 2025-10-24 06:34:26 +0000