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-rw-r--r--VexRiscv/src/test/cpp/raw/machineCsr/.gitignore4
-rw-r--r--VexRiscv/src/test/cpp/raw/machineCsr/build/machineCsr.asm155
-rw-r--r--VexRiscv/src/test/cpp/raw/machineCsr/build/machineCsr.hex37
-rw-r--r--VexRiscv/src/test/cpp/raw/machineCsr/build/machineCsrCompressed.asm155
-rw-r--r--VexRiscv/src/test/cpp/raw/machineCsr/build/machineCsrCompressed.hex37
-rw-r--r--VexRiscv/src/test/cpp/raw/machineCsr/makefile11
-rw-r--r--VexRiscv/src/test/cpp/raw/machineCsr/src/crt.S157
-rw-r--r--VexRiscv/src/test/cpp/raw/machineCsr/src/ld16
8 files changed, 572 insertions, 0 deletions
diff --git a/VexRiscv/src/test/cpp/raw/machineCsr/.gitignore b/VexRiscv/src/test/cpp/raw/machineCsr/.gitignore
new file mode 100644
index 0000000..c12cb2c
--- /dev/null
+++ b/VexRiscv/src/test/cpp/raw/machineCsr/.gitignore
@@ -0,0 +1,4 @@
+*.map
+*.v
+*.elf
+*.o \ No newline at end of file
diff --git a/VexRiscv/src/test/cpp/raw/machineCsr/build/machineCsr.asm b/VexRiscv/src/test/cpp/raw/machineCsr/build/machineCsr.asm
new file mode 100644
index 0000000..679be70
--- /dev/null
+++ b/VexRiscv/src/test/cpp/raw/machineCsr/build/machineCsr.asm
@@ -0,0 +1,155 @@
+
+build/machineCsr.elf: file format elf32-littleriscv
+
+
+Disassembly of section .crt_section:
+
+80000000 <trap_entry-0x20>:
+80000000: 0940006f j 80000094 <_start>
+80000004: 00000013 nop
+80000008: 00000013 nop
+8000000c: 00000013 nop
+80000010: 00000013 nop
+80000014: 00000013 nop
+80000018: 00000013 nop
+8000001c: 00000013 nop
+
+80000020 <trap_entry>:
+80000020: 34202e73 csrr t3,mcause
+80000024: 000e1e63 bnez t3,80000040 <notICmdAlignementException>
+80000028: ffc00f13 li t5,-4
+8000002c: 34102ef3 csrr t4,mepc
+80000030: 01eefeb3 and t4,t4,t5
+80000034: 004e8e93 addi t4,t4,4
+80000038: 341e9073 csrw mepc,t4
+8000003c: 01c0006f j 80000058 <mepcFixed>
+
+80000040 <notICmdAlignementException>:
+80000040: 80000eb7 lui t4,0x80000
+80000044: 01de7f33 and t5,t3,t4
+80000048: 000f1863 bnez t5,80000058 <mepcFixed>
+8000004c: 34102ef3 csrr t4,mepc
+80000050: 004e8e93 addi t4,t4,4 # 80000004 <unalignedPcA+0xfffffe28>
+80000054: 341e9073 csrw mepc,t4
+
+80000058 <mepcFixed>:
+80000058: 80000eb7 lui t4,0x80000
+8000005c: 003e8e93 addi t4,t4,3 # 80000003 <unalignedPcA+0xfffffe27>
+80000060: 01ce9863 bne t4,t3,80000070 <noSoftwareInterrupt>
+80000064: f0013c37 lui s8,0xf0013
+80000068: 00000c93 li s9,0
+8000006c: 019c2023 sw s9,0(s8) # f0013000 <unalignedPcA+0x70012e24>
+
+80000070 <noSoftwareInterrupt>:
+80000070: 80000eb7 lui t4,0x80000
+80000074: 007e8e93 addi t4,t4,7 # 80000007 <unalignedPcA+0xfffffe2b>
+80000078: 01ce9463 bne t4,t3,80000080 <noTimerInterrupt>
+8000007c: 30405073 csrwi mie,0
+
+80000080 <noTimerInterrupt>:
+80000080: 80000eb7 lui t4,0x80000
+80000084: 00be8e93 addi t4,t4,11 # 8000000b <unalignedPcA+0xfffffe2f>
+80000088: 01ce9463 bne t4,t3,80000090 <noExernalInterrupt>
+8000008c: 30405073 csrwi mie,0
+
+80000090 <noExernalInterrupt>:
+80000090: 30200073 mret
+
+80000094 <_start>:
+80000094: 00100e13 li t3,1
+80000098: 00000073 ecall
+8000009c: 00200e13 li t3,2
+800000a0: 00800293 li t0,8
+800000a4: 3002a073 csrs mstatus,t0
+800000a8: 00800293 li t0,8
+800000ac: 30429073 csrw mie,t0
+800000b0: f0013c37 lui s8,0xf0013
+800000b4: 00100c93 li s9,1
+800000b8: 019c2023 sw s9,0(s8) # f0013000 <unalignedPcA+0x70012e24>
+800000bc: 00000013 nop
+800000c0: 00000013 nop
+800000c4: 00000013 nop
+800000c8: 00000013 nop
+800000cc: 00000013 nop
+800000d0: 00000013 nop
+800000d4: 00000013 nop
+800000d8: 00000013 nop
+800000dc: 00000013 nop
+800000e0: 00000013 nop
+800000e4: 00000013 nop
+800000e8: 00000013 nop
+800000ec: 00300e13 li t3,3
+800000f0: 08000293 li t0,128
+800000f4: 30429073 csrw mie,t0
+800000f8: 00000013 nop
+800000fc: 00000013 nop
+80000100: 00000013 nop
+80000104: 00000013 nop
+80000108: 00000013 nop
+8000010c: 00000013 nop
+80000110: 00000013 nop
+80000114: 00400e13 li t3,4
+80000118: 000012b7 lui t0,0x1
+8000011c: 80028293 addi t0,t0,-2048 # 800 <trap_entry-0x7ffff820>
+80000120: 30429073 csrw mie,t0
+80000124: 00000013 nop
+80000128: 00000013 nop
+8000012c: 00000013 nop
+80000130: 00000013 nop
+80000134: 00000013 nop
+80000138: 00000013 nop
+8000013c: 00000013 nop
+80000140: 00500e13 li t3,5
+80000144: f01001b7 lui gp,0xf0100
+80000148: f4018193 addi gp,gp,-192 # f00fff40 <unalignedPcA+0x700ffd64>
+8000014c: 0001a203 lw tp,0(gp)
+80000150: 0041a283 lw t0,4(gp)
+80000154: 3ff20213 addi tp,tp,1023 # 3ff <trap_entry-0x7ffffc21>
+80000158: 0041a423 sw tp,8(gp)
+8000015c: 0051a623 sw t0,12(gp)
+80000160: 00000013 nop
+80000164: 00000013 nop
+80000168: 00000013 nop
+8000016c: 00000013 nop
+80000170: 00000013 nop
+80000174: 00000013 nop
+80000178: 00000013 nop
+8000017c: 00000013 nop
+80000180: 00000013 nop
+80000184: 00000013 nop
+80000188: 00000013 nop
+8000018c: 00000013 nop
+80000190: 00000013 nop
+80000194: 00000013 nop
+80000198: 00600e13 li t3,6
+8000019c: 08000213 li tp,128
+800001a0: 30421073 csrw mie,tp
+800001a4: 00700e13 li t3,7
+800001a8: 10500073 wfi
+800001ac: 00800e13 li t3,8
+800001b0: 00100193 li gp,1
+800001b4: 0041a023 sw tp,0(gp)
+800001b8: 00900e13 li t3,9
+800001bc: 00419023 sh tp,0(gp)
+800001c0: 00a00e13 li t3,10
+800001c4: 0001a203 lw tp,0(gp)
+800001c8: 00b00e13 li t3,11
+800001cc: 00019203 lh tp,0(gp)
+800001d0: 00c00e13 li t3,12
+800001d4: 00d00e13 li t3,13
+800001d8: 00002083 lw ra,0(zero) # 0 <trap_entry-0x80000020>
+
+800001dc <unalignedPcA>:
+800001dc: 0020006f j 800001de <unalignedPcA+0x2>
+800001e0: 00002083 lw ra,0(zero) # 0 <trap_entry-0x80000020>
+800001e4: 00e00e13 li t3,14
+800001e8: 20200073 hret
+800001ec: 00f00e13 li t3,15
+800001f0: f01000b7 lui ra,0xf0100
+800001f4: f6008093 addi ra,ra,-160 # f00fff60 <unalignedPcA+0x700ffd84>
+800001f8: 0000a103 lw sp,0(ra)
+800001fc: 01000e13 li t3,16
+80000200: 0020a023 sw sp,0(ra)
+80000204: 01100e13 li t3,17
+80000208: 00008067 ret
+ ...
diff --git a/VexRiscv/src/test/cpp/raw/machineCsr/build/machineCsr.hex b/VexRiscv/src/test/cpp/raw/machineCsr/build/machineCsr.hex
new file mode 100644
index 0000000..d6c33e7
--- /dev/null
+++ b/VexRiscv/src/test/cpp/raw/machineCsr/build/machineCsr.hex
@@ -0,0 +1,37 @@
+:0200000480007A
+:100000006F004009130000001300000013000000FF
+:100010001300000013000000130000001300000094
+:10002000732E2034631E0E00130FC0FFF32E103406
+:10003000B3FEEE01938E4E0073901E346F00C0012C
+:10004000B70E0080337FDE0163180F00F32E1034EB
+:10005000938E4E0073901E34B70E0080938E3E0038
+:100060006398CE01373C01F0930C000023209C01E3
+:10007000B70E0080938E7E006394CE0173504030A3
+:10008000B70E0080938EBE006394CE017350403053
+:1000900073002030130E100073000000130E2000B8
+:1000A0009302800073A0023093028000739042306C
+:1000B000373C01F0930C100023209C01130000003A
+:1000C00013000000130000001300000013000000E4
+:1000D00013000000130000001300000013000000D4
+:1000E000130000001300000013000000130E300086
+:1000F00093020008739042301300000013000000C8
+:1001000013000000130000001300000013000000A3
+:1001100013000000130E4000B7120000938202800B
+:100120007390423013000000130000001300000021
+:100130001300000013000000130000001300000073
+:10014000130E5000B70110F0938101F403A20100D7
+:1001500083A241001302F23F23A4410023A65100D1
+:100160001300000013000000130000001300000043
+:100170001300000013000000130000001300000033
+:100180001300000013000000130000001300000023
+:100190001300000013000000130E6000130200089B
+:1001A00073104230130E700073005010130E800055
+:1001B0009301100023A04100130E900023904100F2
+:1001C000130EA00003A20100130EB0000392010061
+:1001D000130EC000130ED000832000006F0020001B
+:1001E00083200000130EE00073002020130EF000A7
+:1001F000B70010F0938000F603A10000130E000179
+:1002000023A02000130E10016780000000000000F2
+:1002100000000000000000000000000000000000DE
+:0400000580000094E3
+:00000001FF
diff --git a/VexRiscv/src/test/cpp/raw/machineCsr/build/machineCsrCompressed.asm b/VexRiscv/src/test/cpp/raw/machineCsr/build/machineCsrCompressed.asm
new file mode 100644
index 0000000..097f4e3
--- /dev/null
+++ b/VexRiscv/src/test/cpp/raw/machineCsr/build/machineCsrCompressed.asm
@@ -0,0 +1,155 @@
+
+build/machineCsrCompressed.elf: file format elf32-littleriscv
+
+
+Disassembly of section .crt_section:
+
+80000000 <trap_entry-0x20>:
+80000000: 0940006f j 80000094 <_start>
+80000004: 00000013 nop
+80000008: 00000013 nop
+8000000c: 00000013 nop
+80000010: 00000013 nop
+80000014: 00000013 nop
+80000018: 00000013 nop
+8000001c: 00000013 nop
+
+80000020 <trap_entry>:
+80000020: 34202e73 csrr t3,mcause
+80000024: 000e1e63 bnez t3,80000040 <notICmdAlignementException>
+80000028: ffc00f13 li t5,-4
+8000002c: 34102ef3 csrr t4,mepc
+80000030: 01eefeb3 and t4,t4,t5
+80000034: 004e8e93 addi t4,t4,4
+80000038: 341e9073 csrw mepc,t4
+8000003c: 01c0006f j 80000058 <mepcFixed>
+
+80000040 <notICmdAlignementException>:
+80000040: 80000eb7 lui t4,0x80000
+80000044: 01de7f33 and t5,t3,t4
+80000048: 000f1863 bnez t5,80000058 <mepcFixed>
+8000004c: 34102ef3 csrr t4,mepc
+80000050: 004e8e93 addi t4,t4,4 # 80000004 <unalignedPcA+0xfffffe28>
+80000054: 341e9073 csrw mepc,t4
+
+80000058 <mepcFixed>:
+80000058: 80000eb7 lui t4,0x80000
+8000005c: 003e8e93 addi t4,t4,3 # 80000003 <unalignedPcA+0xfffffe27>
+80000060: 01ce9863 bne t4,t3,80000070 <noSoftwareInterrupt>
+80000064: f0013c37 lui s8,0xf0013
+80000068: 00000c93 li s9,0
+8000006c: 019c2023 sw s9,0(s8) # f0013000 <unalignedPcA+0x70012e24>
+
+80000070 <noSoftwareInterrupt>:
+80000070: 80000eb7 lui t4,0x80000
+80000074: 007e8e93 addi t4,t4,7 # 80000007 <unalignedPcA+0xfffffe2b>
+80000078: 01ce9463 bne t4,t3,80000080 <noTimerInterrupt>
+8000007c: 30405073 csrwi mie,0
+
+80000080 <noTimerInterrupt>:
+80000080: 80000eb7 lui t4,0x80000
+80000084: 00be8e93 addi t4,t4,11 # 8000000b <unalignedPcA+0xfffffe2f>
+80000088: 01ce9463 bne t4,t3,80000090 <noExernalInterrupt>
+8000008c: 30405073 csrwi mie,0
+
+80000090 <noExernalInterrupt>:
+80000090: 30200073 mret
+
+80000094 <_start>:
+80000094: 00100e13 li t3,1
+80000098: 00000073 ecall
+8000009c: 00200e13 li t3,2
+800000a0: 00800293 li t0,8
+800000a4: 3002a073 csrs mstatus,t0
+800000a8: 00800293 li t0,8
+800000ac: 30429073 csrw mie,t0
+800000b0: f0013c37 lui s8,0xf0013
+800000b4: 00100c93 li s9,1
+800000b8: 019c2023 sw s9,0(s8) # f0013000 <unalignedPcA+0x70012e24>
+800000bc: 00000013 nop
+800000c0: 00000013 nop
+800000c4: 00000013 nop
+800000c8: 00000013 nop
+800000cc: 00000013 nop
+800000d0: 00000013 nop
+800000d4: 00000013 nop
+800000d8: 00000013 nop
+800000dc: 00000013 nop
+800000e0: 00000013 nop
+800000e4: 00000013 nop
+800000e8: 00000013 nop
+800000ec: 00300e13 li t3,3
+800000f0: 08000293 li t0,128
+800000f4: 30429073 csrw mie,t0
+800000f8: 00000013 nop
+800000fc: 00000013 nop
+80000100: 00000013 nop
+80000104: 00000013 nop
+80000108: 00000013 nop
+8000010c: 00000013 nop
+80000110: 00000013 nop
+80000114: 00400e13 li t3,4
+80000118: 000012b7 lui t0,0x1
+8000011c: 80028293 addi t0,t0,-2048 # 800 <trap_entry-0x7ffff820>
+80000120: 30429073 csrw mie,t0
+80000124: 00000013 nop
+80000128: 00000013 nop
+8000012c: 00000013 nop
+80000130: 00000013 nop
+80000134: 00000013 nop
+80000138: 00000013 nop
+8000013c: 00000013 nop
+80000140: 00500e13 li t3,5
+80000144: f01001b7 lui gp,0xf0100
+80000148: f4018193 addi gp,gp,-192 # f00fff40 <unalignedPcA+0x700ffd64>
+8000014c: 0001a203 lw tp,0(gp)
+80000150: 0041a283 lw t0,4(gp)
+80000154: 3ff20213 addi tp,tp,1023 # 3ff <trap_entry-0x7ffffc21>
+80000158: 0041a423 sw tp,8(gp)
+8000015c: 0051a623 sw t0,12(gp)
+80000160: 00000013 nop
+80000164: 00000013 nop
+80000168: 00000013 nop
+8000016c: 00000013 nop
+80000170: 00000013 nop
+80000174: 00000013 nop
+80000178: 00000013 nop
+8000017c: 00000013 nop
+80000180: 00000013 nop
+80000184: 00000013 nop
+80000188: 00000013 nop
+8000018c: 00000013 nop
+80000190: 00000013 nop
+80000194: 00000013 nop
+80000198: 00600e13 li t3,6
+8000019c: 08000213 li tp,128
+800001a0: 30421073 csrw mie,tp
+800001a4: 00700e13 li t3,7
+800001a8: 10500073 wfi
+800001ac: 00800e13 li t3,8
+800001b0: 00100193 li gp,1
+800001b4: 0041a023 sw tp,0(gp)
+800001b8: 00900e13 li t3,9
+800001bc: 00419023 sh tp,0(gp)
+800001c0: 00a00e13 li t3,10
+800001c4: 0001a203 lw tp,0(gp)
+800001c8: 00b00e13 li t3,11
+800001cc: 00019203 lh tp,0(gp)
+800001d0: 00c00e13 li t3,12
+800001d4: 00d00e13 li t3,13
+800001d8: 00002083 lw ra,0(zero) # 0 <trap_entry-0x80000020>
+
+800001dc <unalignedPcA>:
+800001dc: 0020006f j 800001de <unalignedPcA+0x2>
+800001e0: 00002083 lw ra,0(zero) # 0 <trap_entry-0x80000020>
+800001e4: 00e00e13 li t3,14
+800001e8: 20200073 hret
+800001ec: 00f00e13 li t3,15
+800001f0: f01000b7 lui ra,0xf0100
+800001f4: f6008093 addi ra,ra,-160 # f00fff60 <unalignedPcA+0x700ffd84>
+800001f8: 0000a103 lw sp,0(ra)
+800001fc: 01000e13 li t3,16
+80000200: 0020a023 sw sp,0(ra)
+80000204: 01100e13 li t3,17
+80000208: 00008067 ret
+ ...
diff --git a/VexRiscv/src/test/cpp/raw/machineCsr/build/machineCsrCompressed.hex b/VexRiscv/src/test/cpp/raw/machineCsr/build/machineCsrCompressed.hex
new file mode 100644
index 0000000..d6c33e7
--- /dev/null
+++ b/VexRiscv/src/test/cpp/raw/machineCsr/build/machineCsrCompressed.hex
@@ -0,0 +1,37 @@
+:0200000480007A
+:100000006F004009130000001300000013000000FF
+:100010001300000013000000130000001300000094
+:10002000732E2034631E0E00130FC0FFF32E103406
+:10003000B3FEEE01938E4E0073901E346F00C0012C
+:10004000B70E0080337FDE0163180F00F32E1034EB
+:10005000938E4E0073901E34B70E0080938E3E0038
+:100060006398CE01373C01F0930C000023209C01E3
+:10007000B70E0080938E7E006394CE0173504030A3
+:10008000B70E0080938EBE006394CE017350403053
+:1000900073002030130E100073000000130E2000B8
+:1000A0009302800073A0023093028000739042306C
+:1000B000373C01F0930C100023209C01130000003A
+:1000C00013000000130000001300000013000000E4
+:1000D00013000000130000001300000013000000D4
+:1000E000130000001300000013000000130E300086
+:1000F00093020008739042301300000013000000C8
+:1001000013000000130000001300000013000000A3
+:1001100013000000130E4000B7120000938202800B
+:100120007390423013000000130000001300000021
+:100130001300000013000000130000001300000073
+:10014000130E5000B70110F0938101F403A20100D7
+:1001500083A241001302F23F23A4410023A65100D1
+:100160001300000013000000130000001300000043
+:100170001300000013000000130000001300000033
+:100180001300000013000000130000001300000023
+:100190001300000013000000130E6000130200089B
+:1001A00073104230130E700073005010130E800055
+:1001B0009301100023A04100130E900023904100F2
+:1001C000130EA00003A20100130EB0000392010061
+:1001D000130EC000130ED000832000006F0020001B
+:1001E00083200000130EE00073002020130EF000A7
+:1001F000B70010F0938000F603A10000130E000179
+:1002000023A02000130E10016780000000000000F2
+:1002100000000000000000000000000000000000DE
+:0400000580000094E3
+:00000001FF
diff --git a/VexRiscv/src/test/cpp/raw/machineCsr/makefile b/VexRiscv/src/test/cpp/raw/machineCsr/makefile
new file mode 100644
index 0000000..4fc2c84
--- /dev/null
+++ b/VexRiscv/src/test/cpp/raw/machineCsr/makefile
@@ -0,0 +1,11 @@
+ifeq ($(COMPRESSED),yes)
+ PROJ_NAME=machineCsrCompressed
+ CFLAGS=-DCOMPRESSED
+else
+ PROJ_NAME=machineCsr
+endif
+
+
+
+
+include ../common/asm.mk \ No newline at end of file
diff --git a/VexRiscv/src/test/cpp/raw/machineCsr/src/crt.S b/VexRiscv/src/test/cpp/raw/machineCsr/src/crt.S
new file mode 100644
index 0000000..91429db
--- /dev/null
+++ b/VexRiscv/src/test/cpp/raw/machineCsr/src/crt.S
@@ -0,0 +1,157 @@
+ j _start
+
+#define writeSoftwareInterrupt(value) \
+ li x24, 0xF0013000; \
+ li x25, value; \
+ sw x25, 0(x24); \
+
+.align 5
+.global trap_entry
+trap_entry:
+ csrr x28, mcause
+
+ bnez x28, notICmdAlignementException
+ li x30, 0xFFFFFFFC
+ csrr x29, mepc
+ and x29,x29,x30
+ addi x29, x29, 4
+ csrw mepc, x29
+ j mepcFixed
+
+notICmdAlignementException:
+ li x29, 0x80000000
+ and x30, x28, x29
+ bnez x30, mepcFixed
+ csrr x29, mepc
+ addi x29, x29, 4
+ csrw mepc, x29
+mepcFixed:
+
+
+ li x29, 0x80000003u
+ bne x29, x28, noSoftwareInterrupt
+ writeSoftwareInterrupt(0)
+
+noSoftwareInterrupt:
+
+ li x29, 0x80000007u
+ bne x29, x28, noTimerInterrupt
+ csrw mie, 0
+noTimerInterrupt:
+
+ li x29, 0x8000000bu
+ bne x29, x28, noExernalInterrupt
+ csrw mie, 0
+noExernalInterrupt:
+
+ mret
+
+
+ .text
+ .globl _start
+_start:
+ li x28, 1
+ ecall
+
+ li x28, 2
+ li t0, 0x008
+ csrs mstatus,t0
+ li t0, 0x008
+ csrw mie,t0
+ writeSoftwareInterrupt(1)
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+
+
+ li x28, 3
+ li t0, 0x080
+ csrw mie,t0
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+
+ li x28, 4
+ li t0, 0x800
+ csrw mie,t0
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+
+ li x28, 5
+ li x3, 0xF00FFF40
+ lw x4, 0(x3)
+ lw x5, 4(x3)
+ addi x4, x4, 1023
+ sw x4, 8(x3)
+ sw x5, 12(x3)
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ li x28, 6
+ li x4, 0x080
+ csrw mie,x4
+ li x28, 7
+ wfi
+
+
+ li x28, 8
+ li x3, 1
+ sw x4,0(x3)
+ li x28, 9
+ sh x4,0(x3)
+ li x28, 10
+ lw x4,0(x3)
+ li x28, 11
+ lh x4,0(x3)
+ li x28, 12
+
+
+
+ li x28, 13
+ lw x1,0(x0)
+#ifndef COMPRESSED
+unalignedPcA:
+ j unalignedPcA+2
+#endif
+ lw x1,0(x0)
+
+ li x28, 14
+ hret
+ li x28, 15
+
+
+ li x1, 0xF00FFF60
+ lw x2, 0(x1)
+ li x28, 16
+ sw x2, 0(x1)
+ li x28, 17
+ jr x1
diff --git a/VexRiscv/src/test/cpp/raw/machineCsr/src/ld b/VexRiscv/src/test/cpp/raw/machineCsr/src/ld
new file mode 100644
index 0000000..93d8de8
--- /dev/null
+++ b/VexRiscv/src/test/cpp/raw/machineCsr/src/ld
@@ -0,0 +1,16 @@
+OUTPUT_ARCH( "riscv" )
+
+MEMORY {
+ onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 128K
+}
+
+SECTIONS
+{
+
+ .crt_section :
+ {
+ . = ALIGN(4);
+ *crt.o(.text)
+ } > onChipRam
+
+}
generated by cgit v1.2.3 (git 2.25.1) at 2025-10-23 22:53:18 +0000